Electrical Characteristics

Electrical Characteristics
(Limits are 100% tested at T_A = +25°C and T_A = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER	SYMBOL	CONDITIONS		MIN	TYP	MAX	UNITS
POWER / BOTH SINGLE-SUPPLY OPERATION AND DUAL-SUPPLY OPERATION
Supply Voltage	V_DD			1.71	1.8	3.63	V
Supply Voltage, Core	V_CORE	Dual-supply operation	OVR = [00]	0.855	0.9	0.945	V
			OVR = [01]	0.95	1.0	1.05
			Default OVR = [10]	1.045	1.1	1.155
		No power supply connection for single-supply operation			—
Supply Voltage, Analog	V_DDA	V_DDA must be connected to V_DD		1.71		3.63	V
Power-Fail Reset Voltage	V_RST	Monitors V_DD		1.58		1.71	V
Power-Fail Reset Voltage	V_RST	Monitors V_CORE during dual-supply operation		0.74		0.845	V
Power-On Reset Voltage	V_POR	Monitors V_DD			1.4		V
Power-On Reset Voltage	V_POR	Monitors V_COREduring dual-supply operation			0.6		V
POWER / SINGLE-SUPPLY OPERATION (V_DD ONLY); f_{SYS_OSC} = IPO
V_DD Current ACTIVE Mode	I_{DD_DACTS}	Dynamic, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)}= 100MHz		62.9		μA/MHz
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)}= 50MHz		64.9
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)}= 12MHz		62.4
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 100MHz		61.4
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 50MHz		63
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 12MHz		60.9
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 100MHz		51.6
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 50MHz		52.1
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 12MHz		50.8
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 100MHz		49.8
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 50MHz		50.4
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 12MHz		49.2
	I_{DD_FACTS}	Fixed, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V		900		μA
			OVR = [01], internal regulator set to 1.0V		751
			OVR = [00], internal regulator set to 0.9V		618
		Fixed, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V		873
			OVR = [01], internal regulator set to 1.0V		729
			OVR = [00], internal regulator set to 0.9V		594
V_DD Current SLEEP Mode	I_{DD_DSLPS}	Dynamic, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 100MHz		36.6		μA/MHz
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 50MHz		38.3
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 12MHz		38.7
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 100MHz		36.5
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 50MHz		37.9
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 12MHz		38.7
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, DMA disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 100MHz		12.5
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 50MHz		11.6
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 12MHz		12.9
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, DMA disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 100MHz		12.7
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 50MHz		12
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 12MHz		14.9
	I_{DD_FSLPS}	Fixed, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V		900		μA
			OVR = [01], internal regulator set to 1.0V		751
			OVR = [00], internal regulator set to 0.9V		618
		Fixed, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V		873
			OVR = [01], internal regulator set to 1.0V		729
			OVR = [00], internal regulator set to 0.9V		594
SLEEP Mode Resume Time	t_{SLP_ONS}	f_{SYS_OSC} = IPO			0.1		μs
DEEPSLEEP Mode Resume Time	t_{DSL_ONS}	f_{SYS_OSC} = IPO	fast_wk_en = 1		74		μs
DEEPSLEEP Mode Resume Time	t_{DSL_ONS}	f_{SYS_OSC} = IPO	fast_wk_en = 0		210		μs
BACKUP Mode Resume Time	t_{BKU_ONS}	f_{SYS_OSC} = IPO, includes system initialization and ROM execution time			1.08		ms
STORAGE Mode Resume Time	t_{STO_ONS}	f_{SYS_OSC} = IPO, includes system initialization and ROM execution time			1.08		ms
POWER / SINGLE-SUPPLY OPERATION (V_DD ONLY); f_{SYS_OSC} = IBRO
V_DD Current ACTIVE Mode	I_{DD_DACTS}	Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)}= 7.3728MHz		78		μA/MHz
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)}= 7.3728MHz		78
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)}= 7.3728MHz		71
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)}= 7.3728MHz		74.6
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)}= 7.3728MHz		74.4
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)}= 7.3728MHz		67.6
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)}= 7.3728MHz		67.5
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)}= 7.3728MHz		66.7
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)}= 7.3728MHz		60.6
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)}= 7.3728MHz		63.7
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)}= 7.3728MHz		62.4
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)}= 7.3728MHz		57.1
	I_{DD_FACTS}	Fixed, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V		423		μA
			OVR = [01], internal regulator set to 1.0V		357
			OVR = [00], internal regulator set to 0.9V		298
		Fixed, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V		376
			OVR = [01], internal regulator set to 1.0V		334
			OVR = [00], internal regulator set to 0.9V		276
V_DD Current SLEEP Mode	I_{DD_DSLPS}	Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		51.8		μA/MHz
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		52
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		48.2
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		51.4
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		50.4
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		46.5
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, DMA disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		27.5
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		26
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		24.6
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, DMA disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		26.8
			OVR = [01], internal regulator set to 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		24.4
			OVR = [00], internal regulator set to 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		23
	I_{DD_FSLPS}	Fixed, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V		423		μA
			OVR = [01], internal regulator set to 1.0V		357
			OVR = [00], internal regulator set to 0.9V		298
		Fixed, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], internal regulator set to 1.1V		376
			OVR = [01], internal regulator set to 1.0V		334
			OVR = [00], internal regulator set to 0.9V		276
SLEEP Mode Resume Time	t_{SLP_ONS}	f_{SYS_OSC} = IBRO			1.1		μs
DEEPSLEEP Mode Resume Time	t_{DSL_ONS}	f_{SYS_OSC} = IBRO	fast_wk_en = 1		182		μs
DEEPSLEEP Mode Resume Time	t_{DSL_ONS}	f_{SYS_OSC} = IBRO	fast_wk_en = 0		319		μs
BACKUP Mode Resume Time	t_{BKU_ONS}	f_{SYS_OSC} = IBRO, includes system initialization and ROM execution time			1.08		ms
STORAGE Mode Resume Time	t_{STO_ONS}	f_{SYS_OSC} = IBRO, includes system initialization and ROM execution time			1.08		ms
POWER / SINGLE-SUPPLY OPERATION (V_DD ONLY)
V_DD Fixed Current, DEEPSLEEP Mode	I_{DD_FDSLS}	Standby state with full data retention and 200KB SRAM retained	V_DD = 3.3V		4.4		μA
V_DD Fixed Current, DEEPSLEEP Mode	I_{DD_FDSLS}		V_DD = 1.8V		4.1		μA
V_DD Fixed Current, BACKUP Mode	I_{DD_FBKUS}	V_DD = 3.3V, RTC disabled	0KB SRAM retained, retention regulator disabled		0.4		μA
			20KB SRAM retained		1.09
			40KB SRAM retained		1.43
			120KB SRAM retained		2.35
			200KB SRAM retained		3.26
		V_DD = 1.8V, RTC disabled	0KB SRAM retained, retention regulator disabled		0.138
			20KB SRAM retained		0.81
			40KB SRAM retained		1.15
			120KB SRAM retained		2.07
			200KB SRAM retained		2.97
V_DD Fixed Current, STORAGE Mode	I_{DD_FSTOS}	V_DD = 3.3V			0.397		μA
V_DD Fixed Current, STORAGE Mode	I_{DD_FSTOS}	V_DD = 1.8V			0.123		μA
POWER / DUAL-SUPPLY OPERATION (V_DD AND V_CORE); f_{SYS_OSC} = IPO
V_CORE Current, ACTIVE Mode	I_{CORE_DACTD}	Dynamic, IPO enabled, total current into V_CORE pin, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SSor V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 100MHz		61.5		μA/MHz
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 50MHz		63.1
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 12MHz		53.2
		Dynamic, IPO enabled, total current into V_CORE pin, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SSor V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 100MHz		50.3
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 50MHz		50.5
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 12MHz		54
	I_{CORE_FACTD}	Fixed, IPO enabled, total current into V_CORE pin, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		497		μA
			OVR = [01], V_CORE = 1.0V		335
			OVR = [00], V_CORE = 0.9V		187
V_DD Current, ACTIVE Mode	I_{DD_DACTD}	Dynamic, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], f_{SYS_CLK(MAX)} = 100MHz		0.005		μA/MHz
			OVR = [01], f_{SYS_CLK(MAX)} = 50MHz		0.004
			OVR = [00], f_{SYS_CLK(MAX)} = 12MHz		0.001
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], f_{SYS_CLK(MAX)} = 100MHz		0.003
			OVR = [01], f_{SYS_CLK(MAX)} = 50MHz		0.0015
			OVR = [00], f_{SYS_CLK(MAX)} = 12MHz		0.001
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], f_{SYS_CLK(MAX)} = 100MHz		0.005
			OVR = [01], f_{SYS_CLK(MAX)} = 50MHz		0.004
			OVR = [00], f_{SYS_CLK(MAX)} = 12MHz		0.001
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], f_{SYS_CLK(MAX)} = 100MHz		0.003
			OVR = [01], f_{SYS_CLK(MAX)} = 50MHz		0.0015
			OVR = [00], f_{SYS_CLK(MAX)} = 12MHz		0.001
	I_{DD_FACTD}	Fixed, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		420		μA
			OVR = [01], V_CORE = 1.0V		420
			OVR = [00], V_CORE = 0.9V		420
		Fixed, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		400
			OVR = [01], V_CORE = 1.0V		400
			OVR = [00], V_CORE = 0.9V		400
V_CORE Current, SLEEP Mode	I_{CORE_DSLPD}	Dynamic, IPO enabled, total current into V_CORE pin, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 100MHz		35.8		μA/MHz
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 50MHz		36.9
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 12MHz		31.4
		Dynamic, IPO enabled, total current into V_CORE pin, CPU in SLEEP mode, ECC disabled, DMA disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 100MHz		12
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 50MHz		11
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 12MHz		9
	I_{CORE_FSLPD}	Fixed, IPO enabled, total current into V_CORE pin, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR [10], V_CORE = 1.1V		497		μA
			OVR [01], V_CORE = 1.0V		335
			OVR [00], V_CORE = 0.9V		187
V_DD Current, SLEEP Mode	I_{DD_DSLPD}	Dynamic, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 100MHz		0.001		μA/MHz
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 50MHz		0.001
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 12MHz		0.001
		Dynamic, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 100MHz		0.001
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 50MHz		0.001
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 12MHz		0.001
	I_{DD_FSLPD}	Fixed, IPO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		420		μA
			OVR = [01], V_CORE = 1.0V		420
			OVR = [00], V_CORE = 0.9V		420
		Fixed, IPO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		400
			OVR = [01], V_CORE = 1.0V		400
			OVR = [00], V_CORE = 0.9V		400
SLEEP Mode Resume Time	t_{SLP_OND}	f_{SYS_OSC} = IPO			0.1		μs
DEEPSLEEP Mode Resume Time	t_{DSL_OND}	f_{SYS_OSC} = IPO	fast_wk_en = 1		37		μs
DEEPSLEEP Mode Resume Time	t_{DSL_OND}	f_{SYS_OSC} = IPO	fast_wk_en = 0		184		μs
BACKUP Mode Resume Time	t_{BKU_OND}	f_{SYS_OSC} = IPO, includes system initialization and ROM execution time			1.05		ms
STORAGE Mode Resume Time	t_{STO_OND}	f_{SYS_OSC} = IPO, includes system initialization and ROM execution time			1.05		ms
POWER / DUAL-SUPPLY OPERATION (V_DD AND V_CORE); f_{SYS_OSC} = IBRO
V_CORE Current, ACTIVE Mode	I_{CORE_DACTD}	Dynamic, IBRO enabled, total current into V_CORE pin, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SSor V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		65.1		μA/MHz
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		65.1
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		54.8
		Dynamic, IBRO enabled, total current into V_CORE pin, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SSor V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		53.1
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		53.1
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		44.1
	I_{CORE_FACTD}	Fixed, IBRO enabled, total current into V_CORE pin, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		280		μA
			OVR = [01], V_CORE = 1.0V		235
			OVR = [00], V_CORE = 0.9V		157
V_DD Current, ACTIVE Mode	I_{DD_DACTD}	Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0054		μA/MHz
			OVR = [01], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0045
			OVR = [00], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0045
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode, executing CoreMark, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0036
			OVR = [01], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0027
			OVR = [00], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0027
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0054
			OVR = [01], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0045
			OVR = [00], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0045
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0036
			OVR = [01], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0027
			OVR = [00], f_{SYS_CLK(MAX)} = 7.3728MHz		0.0027
	I_{DD_FACTD}	Fixed, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		131		μA
			OVR = [01], V_CORE = 1.0V		131
			OVR = [00], V_CORE = 0.9V		131
		Fixed, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in ACTIVE mode 0MHz execution, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		113
			OVR = [01], V_CORE = 1.0V		113
			OVR = [00], V_CORE = 0.9V		113
V_CORE Current, SLEEP Mode	I_{CORE_DSLPD}	Dynamic, IBRO enabled, total current into V_CORE pin, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.06		μA/MHz
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.05
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.036
		Dynamic, IBRO enabled, total current into V_CORE pin, CPU in SLEEP mode, ECC disabled, DMA disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.037
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.027
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.016
	I_{CORE_FSLPD}	Fixed, IBRO enabled, total current into V_CORE pin, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR [10], V_CORE = 1.1V		280		μA
			OVR [01], V_CORE = 1.0V		235
			OVR [00], V_CORE = 0.9V		157
V_DD Current, SLEEP Mode	I_{DD_DSLPD}	Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.0123		μA/MHz
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.0116
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.0116
		Dynamic, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.0123
			OVR = [01], V_CORE = 1.0V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.0116
			OVR = [00], V_CORE = 0.9V, f_{SYS_CLK(MAX)} = 7.3728MHz		0.0116
	I_{DD_FSLPD}	Fixed, IBRO enabled, total current into V_DD pin, V_DD = 3.3V, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		131		μA
			OVR = [01], V_CORE = 1.0V		131
			OVR = [00], V_CORE = 0.9V		131
		Fixed, IBRO enabled, total current into V_DD pin, V_DD = 1.8V, CPU in SLEEP mode, ECC disabled, inputs tied to V_SS or V_DD, outputs source/sink 0mA	OVR = [10], V_CORE = 1.1V		113
			OVR = [01], V_CORE = 1.0V		113
			OVR = [00], V_CORE = 0.9V		113
SLEEP Mode Resume Time	t_{SLP_OND}	f_{SYS_OSC} = IBRO			1.1		μs
DEEPSLEEP Mode Resume Time	t_{DSL_OND}	f_{SYS_OSC} = IBRO	fast_wk_en = 1		146		μs
DEEPSLEEP Mode Resume Time	t_{DSL_OND}	f_{SYS_OSC} = IBRO	fast_wk_en = 0		295		μs
BACKUP Mode Resume Time	t_{BKU_OND}	f_{SYS_OSC} = IBRO, includes system initialization and ROM execution time			1.05		ms
STORAGE Mode Resume Time	t_{STO_OND}	f_{SYS_OSC} = IBRO, includes system initialization and ROM execution time			1.05		ms
POWER / DUAL-SUPPLY OPERATION (V_DD AND V_CORE)
V_CORE Fixed Current, DEEPSLEEP Mode	I_{CORE_FDSLPD}	V_DD = 3.3V, V_CORE = 1.1V			11		μA
		V_DD = 3.3V, V_CORE = 0.855V			4.1
		V_DD = 1.8V, V_CORE = 1.1V			11
		V_DD = 1.8V, V_CORE = 0.855V			4.1
V_DD Fixed Current, DEEPSLEEP Mode	I_{DD_FDSLPD}	V_DD= 3.3V, V_CORE= 1.1V			0.34		μA
		V_DD= 3.3V, V_CORE= 0.855V			0.34
		V_DD= 1.8V, V_CORE= 1.1V			0.11
		V_DD= 1.8V, V_CORE= 0.855V			0.11
V_CORE Fixed Current, BACKUP Mode	I_{CORE_FBKUD}	0KB SRAM retained, RTC disabled, retention regulator disabled	V_DD = 3.3V, V_CORE = 1.1V		0.28		μA
			V_DD = 3.3V, V_CORE = 0.855V		0.15
			V_DD = 1.8V, V_CORE = 1.1V		0.28
			V_DD = 1.8V, V_CORE = 0.855V		0.15
		20KB SRAM retained with RTC disabled	V_DD = 3.3V, V_CORE = 1.1V		1.256
			V_DD = 3.3V, V_CORE = 0.855V		0.52
			V_DD = 1.8V, V_CORE = 1.1V		1.256
			V_DD = 1.8V, V_CORE = 0.855V		0.52
		40KB SRAM retained with RTC disabled	V_DD = 3.3V, V_CORE = 1.1V		2.21
			V_DD = 3.3V, V_CORE = 0.855V		0.881
			V_DD = 1.8V, V_CORE = 1.1V		2.21
			V_DD = 1.8V, V_CORE = 0.855V		0.881
		120KB SRAM retained with RTC disabled	V_DD = 3.3V, V_CORE = 1.1V		5.23
			V_DD = 3.3V, V_CORE = 0.855V		1.91
			V_DD = 1.8V, V_CORE = 1.1V		5.23
			V_DD = 1.8V, V_CORE = 0.855V		1.91
		200KB SRAM retained with RTC disabled	V_DD = 3.3V, V_CORE = 1.1V		8.26
			V_DD = 3.3V, V_CORE = 0.855V		2.94
			V_DD = 1.8V, V_CORE = 1.1V		8.26
			V_DD = 1.8V, V_CORE = 0.855V		2.94
V_DD Fixed Current, BACKUP Mode	I_{DD_FBKUD}	0KB SRAM retained with RTC disabled, retention regulator disabled	V_DD = 3.3V, V_CORE = 1.1V		0.34		μA
			V_DD = 3.3V, V_CORE = 0.855V		0.34
			V_DD = 1.8V, V_CORE = 1.1V		0.12
			V_DD = 1.8V, V_CORE = 0.855V		0.12
		20KB SRAM retained with RTC disabled	V_DD = 3.3V, V_CORE = 1.1V		0.34
			V_DD = 3.3V, V_CORE = 0.855V		0.34
			V_DD = 1.8V, V_CORE = 1.1V		0.12
			V_DD = 1.8V, V_CORE = 0.855V		0.12
		40KB SRAM retained with RTC disabled	V_DD = 3.3V, V_CORE = 1.1V		0.34
			V_DD = 3.3V, V_CORE = 0.855V		0.34
			V_DD = 1.8V, V_CORE = 1.1V		0.12
			V_DD = 1.8V, V_CORE = 0.855V		0.12
		120KB SRAM retained with RTC disabled	V_DD = 3.3V, V_CORE = 1.1V		0.34
			V_DD = 3.3V, V_CORE = 0.855V		0.34
			V_DD = 1.8V, V_CORE = 1.1V		0.12
			V_DD = 1.8V, V_CORE = 0.855V		0.12
		200KB SRAM retained with RTC disabled	V_DD = 3.3V, V_CORE = 1.1V		0.34
			V_DD = 3.3V, V_CORE = 0.855V		0.34
			V_DD = 1.8V, V_CORE = 1.1V		0.12
			V_DD = 1.8V, V_CORE = 0.855V		0.12
V_CORE Fixed Current, STORAGE Mode	I_{CORE_FSTOD}	V_DD = 3.3V, V_CORE = 1.1V			0.284		μA
		V_DD = 3.3V, V_CORE = 0.855V			0.15
		V_DD = 1.8V, V_CORE = 1.1V			0.284
		V_DD = 1.8V, V_CORE = 0.855V			0.15
V_DD Fixed Current, STORAGE Mode	I_{DD_FSTOD}	V_DD = 3.3V; V_CORE = 1.1V			0.385		μA
		V_DD = 3.3V; V_CORE = 0.855V			0.385
		V_DD = 1.8V; V_CORE = 1.1V			0.128
		V_DD = 1.8V; V_CORE = 0.855V			0.128
CLOCKS
System Clock Frequency	f_{SYS_CLK}					100	MHz
System Clock Period	t_{SYS_CLK}				1/f_{SYS_CLK}		μs
Internal Primary Oscillator (IPO)	f_IPO	Default OVR = [10]			100		MHz
External RF Oscillator (ERFO)	f_ERFO	Required crystal characteristics: C_L = 12pF, ESR ≤ 50Ω, C₀ ≤ 7pF, temperature stability ±20ppm, initial tolerance ±20ppm		16		32	MHz
Internal Baud Rate Oscillator (IBRO)	f_IBRO				7.3728		MHz
Internal Nanoring Oscillator (INRO)	f_INRO	Measured at V_DD = 1.8V			70		kHz
External RTC Oscillator (ERTCO)	f_ERTCO	32.768kHz watch crystal, C_L= 6pF, ESR < 90kΩ, C₀ < 2pF			32.768		kHz
RTC Operating Current	I_RTC	All power modes, RTC enabled			0.35		μA
RTC Power-Up Time	t_{RTC_ ON}				250		ms
External Clock Input Frequency	f_{EXT_CLK}	EXT_CLK1 selected				50	MHz
External Clock Input Frequency	f_{EXT_CLK}	EXT_CLK2 selected				1	MHz
12-BIT SAR ADC
Resolution					12		bits
Effective Number of Bits	ENOB	ADC_CLKCTRL.clkdiv = 0bX00. AINx input pk--pk = V_REF – 10mV			10		bits
External Reference Voltage	V_REF	V_REF ≤ V_DDA		2.048		V_DDA	V
Internal Reference Voltage	V_{INT_REF}	MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 0			1.25		V
Internal Reference Voltage	V_{INT_REF}	MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 1			2.048		V
ADC Clock Rate	f_ACLK				1		MHz
ADC Clock Period	t_ACLK				1/f_ACLK		μs
Input Voltage Range	V_AIN	AIN[11:0], ADC_DATA.chan = [11:0]	ADC_CLKCTRL.clkdiv = 0bX00	V_SSA+ 0.05		V_REF	V
			ADC_CLKCTRL.clkdiv = 0bX01	V_SSA+ 0.05		min(2 x V_REF,V_DDA)
			ADC_CLKCTRL.clkdiv = 0bX10	V_SSA+ 0.05		min(2 x V_REF,V_DDA)
Input Impedance	R_AIN	ADC_CLKCTRL.clkdiv = 0bX01			5		kΩ
Input Impedance	R_AIN	ADC_CLKCTRL.clkdiv = 0bX10			50		kΩ
Analog Input Capacitance	C_AIN	Fixed capacitance to V_SSA			2		pF
Analog Input Capacitance	C_AIN	Dynamically switched capacitance			1.2		pF
Integral Nonlinearity	INL				±1.5		LSb
Differential Nonlinearity	DNL				±0.75		LSb
Offset Error	V_OS	Chopping disabled			±9		LSb
Offset Error	V_OS	Chopping enabled			±0.2		LSb
ADC Active Current	I_ADC	ADC active, reference buffer enabled, ADC_CLKCTRL.clkdiv = 0bX00	MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 0, V_DDA = 1.8V		500		µA
			MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 1, V_DDA = 3.3V		788
		ADC active, reference buffer enabled, ADC_CLKCTRL.clkdiv = 0bX01	MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 0, V_DDA = 1.8V		440
			MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 1, V_DDA = 3.3V		670
		ADC active, reference buffer enabled, ADC_CLKCTRL.clkdiv = 0bX10	MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 0, V_DDA = 1.8V		366
			MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 1, V_DDA = 3.3V		512
ADC Sample Rate	f_ADC	ADC_CLKCTRL.clkdiv = 0bX00				1	Msps
		ADC_CLKCTRL.clkdiv = 0bX01				0.625
		ADC_CLKCTRL.clkdiv = 0bX10				0.125
ADC Setup Time	t_{ADC_SU}	Any power-up of ADC clock or ADC bias to CpuAdcStart				500	µs
ADC Input Leakage	I_{ADC_LEAK}	ADC inactive or channel not selected			0.4		nA
Bandgap Temperature Coefficient	V_TEMPCO	Box method			45		ppm
COMPARATORS
Input Offset Voltage	V_OFFSET				±3		mV
Input Hysteresis	V_HYST	AINCOMPHYST[1:0] = 00			22		mV
		AINCOMPHYST[1:0] = 01			50
		AINCOMPHYST[1:0] = 10			2
		AINCOMPHYST[1:0] = 11			7
Input Voltage Range	V_{IN_CMP}	Common-mode range		0.6		1.35	V
GENERAL-PURPOSE I/O
Input Low Voltage for All GPIO, RSTN	V_{IL_GPIO}	Pin configured as GPIO				0.3 × V_DD	V
Input High Voltage for All GPIO, RSTN	V_{IH_GPIO}	Pin configured as GPIO		0.7 × V_DD			V
Output Low Voltage for All GPIO Except P0.6, P0.7, P0.12, P0.13, P0.18, and P0.19	V_{OL_GPIO}	V_DD = 1.71V, I_OL = 1mA, DS[1:0] = 00 (Note 1))			0.2	0.4	V
		V_DD = 1.71V, I_OL = 2mA, DS[1:0] = 10 (Note 1)			0.2	0.4
		V_DD = 1.71V, I_OL = 4mA, DS[1:0] = 01 (Note 1)			0.2	0.4
		V_DD = 1.71V, I_OL = 6mA, DS[1:0] = 11 (Note 1)			0.2	0.4
Output Low Voltage for GPIO P0.6, P0.7, P0.12, P0.13, P0.18, P0.19	V_{OL_I2C}	V_DD = 1.71V, I_OL = 2mA, DS = 0 (Note 1)			0.2	0.4	V
	V_{OL_I2C}	V_DD = 1.71V, I_OL = 8mA, DS = 1 (Note 1)			0.2	0.4	V
Output High Voltage for All GPIO Except P0.6, P0.7, P0.12, P0.13, P0.18, and P0.19	V_{OH_GPIO}	V_DD = 1.71V, I_OH = 1mA, DS[1:0] = 00 (Note 1)		V_DD - 0.4			V
		V_DD = 1.71V, I_OH = 2mA, DS[1:0] = 10 (Note 1)		V_DD - 0.4
		V_DD = 1.71V, I_OH = 4mA, DS[1:0] = 01 (Note 1)		V_DD - 0.4
		V_DD = 1.71V, I_OH = 6mA, DS[1:0] = 11 (Note 1)		V_DD - 0.4
Output High Voltage for GPIO P0.6, P0.7, P0.12, P0.13, P0.18, and P0.19	V_{OH_I2C}	V_DD = 1.71V, I_OH = 2mA, DS = 0 (Note 1)		V_DD - 0.4			V
	V_{OH_I2C}	V_DD = 1.71V, I_OH = 8mA, DS = 1 (Note 1)		V_DD - 0.4			V
Combined I_OL, All GPIO	I_{OL_TOTAL}					100	mA
Combined I_OH, All GPIO	I_{OH_TOTAL}			-100			mA
Input Hysteresis (Schmitt)	V_IHYS				300		mV
Input/Output Pin Capacitance for All Pins	C_IO				4		pF
Input Leakage Current Low	I_IL	V_IN = 0V, internal pullup disabled		-500		+500	nA
Input Leakage Current High	I_IH	V_IN = 3.6V, internal pulldown disabled		-500		+500	nA
Input Pullup Resistor to RSTN	R_{PU_VDD}	Pullup to V_DD = V_RST, RSTN at V_IH			18.7		kΩ
Input Pullup Resistor to RSTN	R_{PU_VDD}	Pullup to V_DD = 3.63V, RSTN at V_IH			10.0		kΩ
Input Pullup Resistor for All GPIO	R_PU	Device pin configured as GPIO, pullup to V_DD = V_RST, device pin at V_IH			18.7		kΩ
Input Pullup Resistor for All GPIO	R_PU	Device pin configured as GPIO, pullup to V_DD = 3.63V, device pin at V_IH			10.0		kΩ
Input Pulldown Resistor for All GPIO	R_PD	Device pin configured as GPIO, pulldown to V_SS, V_DD = V_RST, device pin at V_IL			17.6		kΩ
Input Pulldown Resistor for All GPIO	R_PD	Device pin configured as GPIO, pulldown to V_SS, V_DD = 3.63V, device pin at V_IL			8.8		kΩ
FLASH MEMORY
Flash Erase Time	t_{M_ERASE}	Mass erase			30		ms
Flash Erase Time	t_{P_ERASE}	Page erase			30		ms
Flash Programming Time per Word	t_PROG	32-bit programming mode, f_{FLC_CLK} = 1MHz			42		μs
Flash Endurance				10			kcycles
Data Retention	t_RET	T_A = +125°C		10			years

Electrical Characteristics—SPI
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
MASTER MODE
SPI Master Operating Frequency	f_MCK	f_{SYS_CLK}= 100MHz, f_MCK(MAX)= f_{SYS_CLK}/2			50	MHz
SPI Master SCK Period	t_MCK			1/f_MCK		ns
SCK Output Pulse-Width High/Low	t_MCH, t_MCL		t_MCK/2			ns
MOSI Output Hold Time After SCK Sample Edge	t_MOH		t_MCK/2			ns
MOSI Output Valid to Sample Edge	t_MOV		t_MCK/2			ns
MOSI Output Hold Time After SCK Low Idle	t_MLH			t_MCK/2		ns
MISO Input Valid to SCK Sample Edge Setup	t_MIS			5		ns
MISO Input to SCK Sample Edge Hold	t_MIH			t_MCK/2		ns
SLAVE MODE
SPI Slave Operating Frequency	f_SCK				50	MHz
SPI Slave SCK Period	t_SCK			1/f_SCK		ns
SCK Input Pulse-Width High/Low	t_SCH, t_SCL			t_SCK/2
SSx Active to First Shift Edge	t_SSE			10		ns
MOSI Input to SCK Sample Edge Rise/Fall Setup	t_SIS			5		ns
MOSI Input from SCK Sample Edge Transition Hold	t_SIH			1		ns
MISO Output Valid after SCLK Shift Edge Transition	t_SOV			5		ns
SCK Inactive to SSx Inactive	t_SSD			10		ns
SSx Inactive Time	t_SSH			1/f_SCK		μs
MISO Hold Time after SSx Deassertion	t_SLH			10		ns

Electrical Characteristics—I²C
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
STANDARD MODE
Output Fall Time	t_OF	Standard mode, from V_IH(MIN) to V_IL(MAX)		150		ns
SCL Clock Frequency	f_SCL		0		100	kHz
Low-Period SCL Clock	t_LOW		4.7			μs
High-Time SCL Clock	t_HIGH		4.0			μs
Setup Time for Repeated Start Condition	t_SU;STA		4.7			μs
Hold Time for Repeated Start Condition	t_HD;STA		4.0			μs
Data Setup Time	t_SU;DAT			300		ns
Data Hold Time	t_HD;DAT			10		ns
Rise Time for SDA and SCL	t_R			800		ns
Fall Time for SDA and SCL	t_F			200		ns
Setup Time for a Stop Condition	t_SU;STO		4.0			μs
Bus Free Time Between a Stop and Start Condition	t_BUS		4.7			μs
Data Valid Time	t_VD;DAT		3.45			μs
Data Valid Acknowledge Time	t_VD;ACK		3.45			μs
FAST MODE
Output Fall Time	t_OF	From V_IH(MIN) to V_IL(MAX)		150		ns
Pulse Width Suppressed by Input Filter	t_SP			75		ns
SCL Clock Frequency	f_SCL		0		400	kHz
Low-Period SCL Clock	t_LOW		1.3			μs
High-Time SCL Clock	t_HIGH		0.6			μs
Setup Time for Repeated Start Condition	t_SU;STA		0.6			μs
Hold Time for Repeated Start Condition	t_HD;STA		0.6			μs
Data Setup Time	t_SU;DAT			125		ns
Data Hold Time	t_HD;DAT			10		ns
Rise Time for SDA and SCL	t_R			30		ns
Fall Time for SDA and SCL	t_F			30		ns
Setup Time for a Stop Condition	t_SU;STO		0.6			μs
Bus Free Time Between a Stop and Start Condition	t_BUS		1.3			μs
Data Valid Time	t_VD;DAT		0.9			μs
Data Valid Acknowledge Time	t_VD;ACK		0.9			μs
FAST MODE PLUS
Output Fall Time	t_OF	From V_IH(MIN) to V_IL(MAX)		80		ns
Pulse Width Suppressed by Input Filter	t_SP			75		ns
SCL Clock Frequency	f_SCL		0		1000	kHz
Low-Period SCL Clock	t_LOW		0.5			μs
High-Time SCL Clock	t_HIGH		0.26			μs
Setup Time for Repeated Start Condition	t_SU;STA		0.26			μs
Hold Time for Repeated Start Condition	t_HD;STA		0.26			μs
Data Setup Time	t_SU;DAT			50		ns
Data Hold Time	t_HD;DAT			10		ns
Rise Time for SDA and SCL	t_R			50		ns
Fall Time for SDA and SCL	t_F			30		ns
Setup Time for a Stop Condition	t_SU;STO		0.26			μs
Bus Free Time Between a Stop and Start Condition	t_BUS		0.5			μs
Data Valid Time	t_VD;DAT		0.45			μs
Data Valid Acknowledge Time	t_VD;ACK		0.45			μs

Electrical Characteristics—I²S Slave
(Timing specifications are guaranteed by design and not production tested, T_A = -40°C to +105°C.)
PARAMETER	SYMBOL	MIN	TYP	MAX	UNITS
Bit Clock Frequency	f_BCLKS			25	MHz
Bit Clock Period	t_BCLKS	1/f_BCLKS			ns
BCLK High Time	t_WBCLKHS		0.5		1/f_BCLKS
BCLK Low Time	t_WBCLKLS		0.5		1/f_BCLKS
LRCLK Setup Time	t_{LRCLK_BCLKS}		25		ns
Delay Time, BCLK to SD (Output) Valid	t_{BCLK_SDOS}		12		ns
Setup Time for SD (Input)	t_{SU_SDIS}		6		ns
Hold Time SD (Input)	t_{HD_SDIS}		3		ns

Electrical Characteristics—Quadrature Decoder
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
Encoder Period	t_EP	Ensure at least one sample in each encoder state	4	8		t_PCLK
Encoder Pulse Width	t_E	Ensure at least one sample in each encoder state	2	4		t_PCLK
Encoder State Period	t_ES	Ensure at least one sample in each encoder state	1	2		t_PCLK
Index Signal Width	t_IND		1	1/4 x t_EP	t_EP	t_PCLK
Expected Glitch Time Window	t_GL	QDEC_CTRL.filter = 0b00	0			t_PCLK
Expected Glitch Time Window	t_GL	QDEC_CTRL.filter = 0b01		1		t_PCLK
Q DIRECTION	t_QDIR	After either QEA or QEB transition		4		t_PCLK
Q MATCH	t_QM	After either QEA or QEB transition		4		t_PCLK
Q MATCH Pulse Width	t_QMP	Until next state transition		1		t_ES
Q ERROR	t_ER	After either a faulty QEA or QEB transition		4		t_PCLK
Q ERROR Pulse Width	t_ERP	Until next state transition		1		t_ES

GPIO Drive Strength:	Note 1: When using a GPIO bias voltage of 2.97V, the drive current capability of the GPIO is 2x that of its drive strength when using a GPIO bias voltage of 1.62V.
Figure 1. Power Supply Operational Modes
Figure 2. SPI Master Mode Timing Diagram
Figure 3. SPI Slave Mode Timing Diagram
Figure 4. I²C Timing Diagram
Figure 5. I²S Timing Diagram
Figure 6. Quadrature Decoder Timing Diagram

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 1)\u003c/strong\u003e","data-html":true,"data-content":"Note 1: When using a GPIO bias voltage of 2.97V, the drive current capability of the GPIO is 2x that of its drive strength when using a GPIO bias voltage of 1.62V."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 1\u003c/strong\u003e","data-html":true,"data-content":"Note 1: When using a GPIO bias voltage of 2.97V, the drive current capability of the GPIO is 2x that of its drive strength when using a GPIO bias voltage of 1.62V."}