Detailed Description

The MAX32672 is an ultra-low-power, cost-effective, highly integrated microcontroller designed for battery-powered devices and wireless sensors. It combines a flexible and versatile power management unit with the powerful Arm Cortex-M4 processor with FPU. The device enables designs with complex sensor processing without compromising battery life. It also offers legacy designs an easy and cost-optimal upgrade path from 8- or 16-bit microcontrollers. Error correction coding (single error correction, double error detection, or SEC-DED) for flash and SRAM provides extremely reliable code execution. The device integrates 1MB of dual-bank flash memory and 200KB (160KB with ECC enabled) of SRAM to accommodate application and sensor code. A 1Msps, 12-channel, 12-bit SAR ADC is integrated for the digitization of analog sensor signals or other analog measurements.

The device features five powerful and flexible power modes. It can operate from a single-supply battery or a dual-supply typically provided by a PMIC. The I²C ports support standard, fast, fast-plus, and high-speed modes, operating up to 3400kbps. The SPI ports can run up to 50MHz in both master and slave mode. Four general-purpose 32-bit timers, two low-power 32-bit timers, two windowed watchdog timers, and a real-time clock (RTC) are also provided. An I²S interface provides digital audio streaming to a codec.

Arm Cortex-M4 Processor with FPU Engine

The Arm Cortex-M4 with FPU processor combines high-efficiency signal processing functionality with low power, low cost, and ease of use.

The Arm Cortex-M4 with FPU DSP supports single instruction, multiple data (SIMD) path DSP extensions, providing:

Four parallel 8-bit add/sub
Floating point single precision
Two parallel 16-bit add/sub
Two parallel MACs
32- or 64-bit accumulate
Signed, unsigned, data with or without saturation

Memory

Internal Flash Memory

The 1MB internal flash memory with error correction provides nonvolatile storage of program and data memory. The flash is organized in two equal sizes, physically separate banks (dual bank) to allow execute-while-write operation and facilitate "live FW upgrades."

Internal SRAM

The internal 200KB SRAM provides low-power retention of application information in all power modes except STORAGE. The SRAM can be configured as 160KB with error correction coded (ECC) SEC-DED for enhanced system reliability. The SRAM can be divided into granular banks that create a flexible SRAM retention architecture. This data retention feature is optional and is configurable. This granularity allows the application to minimize its power consumption by only retaining the essential data.

Clocking Scheme

The internal primary oscillator (IPO) operates at a nominal frequency of 100MHz.

Optionally, the software can select one of five other oscillators depending upon power needs:

80kHz oscillator (INRO)
32.768kHz oscillator (external crystal required) (ERTC0)
7.3728MHz oscillator (IBRO)
16MHz–32MHz oscillator (external crystal required) (ERFO)
External square-wave clocks up to 50MHz

This clock is the primary clock source for digital logic and peripherals.

An external 32.768kHz timebase is required when using the RTC. A separate external square-wave clock can be used as a source for LPTMR0/1 and LPUART0 in the Always-ON domain.

General-Purpose I/O and Special Function Pins

Most general-purpose I/O (GPIO) pins share both a firmware-controlled I/O function and one or more special function signals associated with peripheral modules. Software can individually enable pins for GPIO or peripheral special function use. Configuring a pin as a special function usually supersedes its use as a software-controlled I/O. Multiplexing between peripheral and GPIO functions is usually static but can also be done dynamically by software. The electrical characteristics of a GPIO pin are identical whether the pin is configured as an I/O or special function, except where explicitly noted in the Electrical Characteristics tables.

In GPIO mode, each pin of a port has an interrupt function that can be independently enabled by software and configured as a level- or edge-sensitive interrupt. All GPIOs share the same interrupt vector. Some packages do not have all of the GPIOs available.

When configured as GPIOs, the following features are provided. These features can be independently enabled or disabled on a per-pin basis.

Configurable as input, output, bidirectional, or high-impedance
Optional internal pullup resistor or internal pulldown resistor when configured as input
Exit from low-power modes on rising or falling edge
Selectable standard- or high-drive modes

The MAX32672 provides up to 28 GPIOs for the 40-pin TQFN.

Standard DMA Controller

The standard direct memory access (DMA) controller provides a means to offload the CPU for memory/peripheral data transfer leading to a more power-efficient system. It allows automatic one-way data transfer between two entities. These entities can be either memories or peripherals. The transfers are done without using CPU resources. The following transfer modes are supported:

12 channel
Peripheral to data memory
Data memory to peripheral
Data memory to data memory
Event support

All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from the FIFO.

Power Management

Power Management Unit

The power management unit (PMU) provides the optimal mix of high-performance and low-power consumption. It exercises intelligent, precise control of power distribution to the CPU and peripheral circuitry.

The PMU provides the following features:

User-configurable system clock
Automatic enabling and disabling of crystal oscillators based on power mode
Multiple clock domains
Fast wakeup of powered-down peripherals when activity detected

ACTIVE Mode

In this mode, the CPU executes software and all digital and analog peripherals are available on demand. Dynamic clocking disables local clocks in peripherals that are not in use. This mode corresponds to the Arm Cortex-M4 processor with FPU ACTIVE mode.

SLEEP Mode

This mode allows for lower power consumption operations than ACTIVE mode. The CPU is asleep, peripherals are on, and the standard DMA block is available. The GPIO or any active peripheral can be configured to interrupt and cause a transition to the ACTIVE mode. This mode corresponds to the Arm Cortex-M4 processor with FPU SLEEP mode.

DEEPSLEEP Mode

In this mode, CPU and critical peripheral configuration settings and all volatile memory are preserved.

The device status is as follows:

CPU is powered down. System state and all SRAM is retained.
The GPIO pins retain their state.
The transition from DEEPSLEEP to ACTIVE mode is faster than the transition from BACKUP mode because system initialization is not required.
The system oscillators are all disabled to provide additional power savings over SLEEP mode.
LPUART0 and LPTMR0/1 can be active and are optional wake-up sources.

This mode corresponds to the Arm Cortex-M4 with FPU DEEPSLEEP mode.

BACKUP Mode

This mode places the CPU in a static, low-power state. The BACKUP mode supports the same wake-up sources as DEEPSLEEP mode.

The device status is as follows:

CPU is powered down.
SRAM retention as per Table 1.
LPUART0 and LPTMR0/1 can be active and are optional wake-up sources.

Table 1. BACKUP Mode RAM Retention
RAM BLOCK	RAM SIZE	TYPE
SYSRAM0	20KB	16KB + 4KB ECC
SYSRAM1	20KB	16KB + 4KB ECC
SYSRAM2	80KB	64KB + 16KB ECC
SYSRAM3	80KB	64KB + 16KB ECC

STORAGE Mode

The device status is as follows:

CPU is powered off.
All peripherals are powered off.
Wake-up from GPIO interrupt.
The RTC can be enabled by software before entering STORAGE mode.
No SRAM retention.

Real-Time Clock (RTC)

An RTC keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by application software.

The RTC provides a time-of-day alarm programmed by software to any future value between 1 second and 12 days. When configured for long intervals, the time-of-day alarm can be used as a power-saving timer, allowing the device to remain in an extremely low-power mode but still awaken periodically to perform assigned tasks. Software can program a second independent 32-bit 1/4096 sub-second alarm between 244μs and 12 days. Both can be configured as recurring alarms. When enabled, either alarm can cause an interrupt or wake the device from most low-power modes.

The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing requirements in the Electrical Characteristics table.

An RTC calibration feature allows the software to compensate for minor variations in the RTC oscillator, crystal, temperature, and board layout. Enabling the 32KCAL alternate function outputs a timing signal derived from the RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with a 1ppm resolution. Under most circumstances, the oscillator does not require any calibration.

Windowed Watchdog Timer (WDT)

Microcontrollers are often used in harsh environments where electrical noise and electromagnetic interference (EMI) are abundant. Without proper safeguards, these hazards can disturb device operation and corrupt program execution. One of the most effective countermeasures is the windowed WDT, which detects runaway code or system unresponsiveness.

The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically reset by the application software. Failure to reset the WDT within the user-configurable timeout period indicates that the application software is not operating correctly and results in a WDT timeout. A WDT timeout can trigger an interrupt, system reset, or both. Either response forces the instruction pointer to a known good location before resuming instruction execution. The windowed timeout period feature provides more detailed monitoring of system operation, requiring the WDT to be reset within a specific time window.

The WDT supports multiple clock option:

100MHz oscillator
16MHz–32MHz (external crystal required)
7.3728MHz oscillator
80kHz oscillator
32.768kHz oscillator (external crystal required)
External square-wave clocks up to 50MHz
Pixel clock (PCLK)

The MAX32672 provides two instances of the windowed watchdog timer: WDT0 and WDT1.

32-Bit Timer/Counter/PWM (TMR, LPTMR)

General-purpose, 32-bit timers provide timing, capture/compare, or generate pulse-width modulated (PWM) signals with minimal software interaction.

The timer provides the following features:

32-bit up/down auto-reload
Programmable prescaler
PWM output generation
Capture, compare, and capture/compare capability
External pin multiplexed with GPIO for timer input, clock gating, or capture
Timer output pin
TMR0-TMR3 configurable as 2 × 16-bit general-purpose timers
Timer interrupt

The MAX32672 provides six 32-bit timers (TMR0, TMR1, TMR2, TMR3, LPTMR0, LPTMR1). The LPTMR0 and LPTMR1 are capable of operation in the SLEEP, DEEPSLEEP, and BACKUP low-power modes.

The I/O functionality is supported for all of the timers. Note that the function of a port can be multiplexed with other functions on the GPIO pins, so it might not be possible to use all the ports depending on the device configuration. See Table 2 for individual timer features.

Table 2. Timer Configuration Options
INSTANCE	32-BIT ONLY	DUAL 16-BIT	MODE	CLOCK SOURCE
INSTANCE	32-BIT ONLY	DUAL 16-BIT	MODE	PCLK	7.3728MHz	16MHz–32MHz	80kHz	32.768kHz	EXT_CLK1	EXT_CLK2
TMR0	YES	YES	ACTIVE	YES	YES	YES	NO	NO	YES	NO
TMR1	YES	YES	ACTIVE	YES	YES	YES	NO	NO	YES	NO
TMR2	YES	YES	ACTIVE	YES	YES	YES	NO	NO	YES	NO
TMR3	YES	YES	ACTIVE	YES	YES	YES	NO	NO	YES	NO
LPTMR0	YES	NO	ACTIVE/SLEEP/ DEEPSLEEP/BACKUP	YES	NO	NO	YES	YES	NO	YES
LPTMR1	YES	NO	ACTIVE/SLEEP/ DEEPSLEEP/BACKUP	YES	NO	NO	YES	YES	NO	YES

Serial Peripherals

I²C Interface

The I²C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can operate as a one-to-one, one-to-many, or many-to-many communications medium. These engines support standard-mode, fast-mode, fast-mode plus, and high-speed mode I²C speeds. It provides the following features:

Master or slave mode operation
- Supports up to four different slave addresses in slave mode
Supports standard 7-bit addressing or 10-bit addressing
RESTART condition
Interactive receive mode
Tx FIFO preloading
Support for clock stretching to allow slower slave devices to operate on higher speed busses
Multiple transfer rates
- Standard mode: 100kbps
- Fast mode: 400kbps
- Fast mode plus: 1000kbps
- High-speed mode: 3400kbps
Internal filter to reject noise spikes
Receiver FIFO depth of 8 bytes
Transmitter FIFO depth of 8 bytes

The MAX32672 provides three instances of the I²C peripheral (I2C0, I2C1, and I2C2).

Serial Peripheral Interface (SPI)

The SPI is a highly configurable, flexible, and efficient synchronous interface between multiple SPI devices on a single bus. The bus uses a single clock signal and multiple data signals and one or more slave select lines to address only the intended target device. The SPI operates independently and requires minimal processor overhead.

The provided SPI peripherals can operate in either slave or master mode and provide the following features:

SPI modes 0, 1, 2, and 3 for single-bit communication
3- or 4-wire mode for single-bit slave device communication
Full-duplex operation in single-bit, 4-wire mode
Multimaster mode fault detection
Programmable interface timing
Programmable SCK frequency and duty cycle
32-byte transmit and receive FIFOs
Slave select assertion and deassertion timing relative to leading/trailing SCK edge

The MAX32672 provides two instances of this SPI peripheral (SPI0 and SPI1). See Table 3 for configuration options.

Table 3. SPI Configuration Options
INSTANCE	DATA	SLAVE SELECT LINES	MAXIMUM FREQUENCY (MASTER MODE) (MHz)	MAXIMUM FREQUENCY (SLAVE MODE) (MHz)
SPI0	3 wire, 4 wire	4	50	50
SPI1	3 wire, 4 wire	1	50	50

I²S Interface

The I²S interface is a bidirectional, 4-wire serial bus that provides serial communications for codecs and audio amplifiers compliant with the I²S Bus Specification, June 5, 1996. It provides the following features:

Slave mode operation
Support for four channels
8-, 16-, 24-, and 32-bit frames
Receive and transmit DMA support
Wakeup on FIFO status (full/empty/threshold)
Pulse density modulation support for the receive channel
Word select polarity control
First-bit position selection
Interrupts generated for FIFO status
Receiver FIFO depth of 32 bytes
Transmitter FIFO depth of 32 bytes

The MAX32672 provides one instance of the I²S peripheral (I2S0).

UART

The universal asynchronous receiver-transmitter (UART, LPUART) interface supports full-duplex asynchronous communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a given port, the system uses two extra pins to implement the industry-standard request-to-send (RTS) and clear-to-send (CTS) flow control signaling. Each LPUART is individually programmable.

2-wire interface or 4-wire interface with flow control
8-byte send/receive FIFO
Full-duplex operation for asynchronous data transfers
Interrupts available for frame error, parity error, CTS, Rx FIFO overrun, and FIFO full/partially full conditions
Automatic parity and frame error detection
Independent baud-rate generator
Programmable 9th-bit parity support
Multidrop support
Start/stop bit support
Hardware flow control using RTS/CTS
Two DMA channels can be connected (read and write FIFOs)
Programmable word size (5 bits to 8 bits)

The MAX32672 provides four instances of the UART peripheral (UART0, UART1, UART2, and LPUART0). LPUART0 is capable of operation in the SLEEP, DEEPSLEEP, and BACKUP low-power modes. See Table 4 for configuration options.

Table 4. UART Configuration Options
INSTANCE	MODE	CLOCK SOURCE
INSTANCE	MODE	PCLK	7.3728MHz	16MHz–32MHz	80kHz	32.768kHz	EXT_CLK1	EXT_CLK2
UART0	ACTIVE	YES	YES	YES	NO	NO	YES	NO
UART1	ACTIVE	YES	YES	YES	NO	NO	YES	NO
UART2	ACTIVE	YES	YES	YES	NO	NO	YES	NO
LPUART0	ACTIVE/SLEEP/ DEEPSLEEP/BACKUP	ALWAYS-ON DOMAIN CLOCK	NO	NO	YES	YES	NO	YES

Quadrature Decoder

The quadrature decoder converts rotational information derived from optical or magnetic encoders to counts representing a shaft's angle and rotational velocity.

The following features are provided:

x1, x2, and x4 mode selection
32-bit counter
Index input
Rotational direction and error outputs
On-chip deglitch filters

Analog-to-Digital Converter (ADC)

The 12-bit SAR ADC provides an integrated reference generator and a single-ended input multiplexer. The multiplexer selects an input channel from one of the 12 external analog input signals (AIN0–AIN11), the internal power supply inputs, or an internal temperature sensor.

The reference for the ADC can be:

External V_REF input
V_DDA analog supply

The ADC measures the following voltages:

AIN[11:0] up to 3.3V
V_DD
V_CORE
V_DDA
Internal die temperature sensor input

Security

AES

The dedicated hardware-based AES engine supports the following algorithms:

AES-128
AES-192
AES-256

The AES keys are automatically generated by the engine and stored in a dedicated flash region to protect against tampering. Key generation and storage are transparent to the user.

True Random Number Generator (TRNG)

Random numbers are a vital part of a secure application, providing random numbers useable for cryptographic seeds or strong encryption keys to ensure data privacy.

Software can use random numbers to trigger asynchronous events that result in nondeterministic behavior. This helps thwart replay attacks or key search approaches. A high-entropy source must continuously update an effective TRNG.

A physically unpredictable entropy source continuously drives the provided TRNG. It generates a 128-bit true random number in 128 system clock cycles.

The TRNG can support the system-level validation of many security standards such as FIPS 140-2, PCI-PED, and Common Criteria. Contact Maxim for details of compliance with specific standards.

CRC Module

A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application software. The CRC module supports the following polynomials:

CRC-16-CCITT
CRC-32 (X³² + X²⁶+ X²³+ X²²+ X¹⁶+ X¹²+ X¹¹+ X¹⁰+ X⁸ + X⁷+ X⁵+ X⁴+ X²+ X + 1)

Root of Trust

The root of trust starts with trusted software and the microcontroller's complement of security features. Communications between a host and the device must be secure and authenticated, and program integrity must be verified each time before execution to ensure the device's trustworthiness. The device's root of trust is based on a Maxim Integrated master root verification key and a signed customer verification key (CVK). Customers submit their public CVK to Maxim Integrated, which is then signed, and this public key is sent back to the customer. This process is quick and required only once, before the software is released for the first time, and is unnecessary during the software development. A customer can then load their own key and download their signed binary executable code. A life-cycle scheme allows the device to be permanently disabled to deactivate a deployed application.

Secure Communications Protocol Bootloader (SCPBL)

Communication between a host system and the device uses a system of digitally signed packets. This guarantees the integrity and authenticity of all communication before executing configuration commands and the loading or verification of program memory. One or more serial interfaces are available for communication. This also enables the assembly and programming of the customer's final product by third-party assembly houses without the required cost and complexity of ensuring that the assembly house implements and maintains a secure production facility. It also allows for in-field software upgrades to deployed products, thus eliminating the costly need to return a product to the manufacturer for any software changes.

The serial interfaces available for SCPBL communication are shown in Table 5. Following any reset, the device will test the assigned stimulus pin and, if active, begin an SCPBL session. Unless otherwise specified, the SCPBL must first be configured through the default interface to activate any other interfaces and/or redefined stimulus pins other than the default assignment. Software can disable the bootloader interface before deployment to prevent any changes to program memory.

Secure Boot

Following every reset, the device performs a secure boot to confirm the root of trust has not been compromised. The secure boot verifies the digital signature of the program memory to confirm it has not been modified or corrupted, ensuring the trustworthiness of the application software. Failure to verify the digital signature will transition the device to safe mode, which prevents execution of the customer code. During the development phase, the bootloader can be reactivated and a new, trusted program memory loaded.

Debug and Development Interface

The serial wire debug (SWD) interface is used for code loading and in-circuit emulator (ICE) debug activities. All devices in mass production have the debugging/development interface enabled.