Package Information

24 TQFN-EP

Package Code	T2433+2C
Outline Number	21-100264
Land Pattern Number	90-100089
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ_JA)	61.3°C/W
Junction to Case (θ_JC)	2.2°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

data-opMAX32663AGTGFS%2BT

data-opMAX32663AGTGFS%2B

This pin must be bypassed to VSS with a 1.0μF capacitor as close as possible to the package. The device operates solely from this one power supply pin.VCORE must always be bypassed to VSS with a 1.0μF capacitor as close as possible to the package. Do not connect this device pin to any other circuits.—Exposed Pad (TQFN Only). This pad must be connected to VSS. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.Connect a 32.768kHz crystal between 32KIN and 32KOUT for RTC operation. Optionally, an external clock source can be driven on 32KIN if the 32KOUT pin is left unconnected.—External System Reset (Active-Low) Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a reset (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. This pin is internally connected with an internal pullup to the VDD supply as indicated in the Electrical Characteristics table. Add and place a noise snubber circuit as close as possible to the device with component values shown in the Typical Application Circuit.This is the SPI master clock output that should be connected to the MAX30003 SCLK input.This is the SPI master-in, slave-out that should be connected to the MAX30003 SDO pin.This is the SPI master-out, slave-in that should be connected to the MAX30003 SDI pin.This is the SPI master chip select output that should be connected to the MAX30003 CSB input.This is the I2C slave SCL that should be connected to the host I2C master SCL.This is the I2C slave SDA that should be connected to the host I2C master SDA.This pin is an active-low interrupt input. It connects to the INT2B interrupt output of the MAX30003.This pin is an active-low interrupt input. It connects to the INTB interrupt output of the MAX30003.This pin is asserted low by the MAX32663A when the device requires servicing through the I2C interface.This pin is internally connected. Do not make any electrical connection, including VSS, to this pin.This pin is not connected to the die and can be used to route any signal.