| PIN | NAME | FUNCTION MODE | FUNCTION | ||
| Primary Signal (Default) | Alternate Function 1 | Alternate Function 2 | |||
| POWER (See the Applications Information section for bypass capacitor recommendations.) | |||||
| C9, B4 | VREGI | — | — | — | Battery Power Supply for the SIMO Switch-Mode Power Supply (SMPS). Bypass device pin C9 with 2 x 47μF capacitors placed as close as possible to the device pin C9 and VSSPWR pins for applications using a coin cell as the battery. See Bypass Capacitors for more information. If power to the device is cycled, the voltage applied to this device pin must reach VREGI (rising). |
| B3 | BLE_LDO_IN | — | — | — | Bluetooth LDO Input. Bypass BLE_LDO_IN with a 100nF capacitor to VSS placed as close as possible to the BLE_LDO_IN device pin. |
| B5 | VDDA | — | — | — | 1.8V Analog Power Supply |
| D9 | VCOREA | — | — | — | Digital Core Supply Voltage A |
| C8 | VCOREB | — | — | — | Digital Core Supply Voltage B |
| B1 | VRXOUT | — | — | — | Radio Receiver Supply Voltage Output. Bypass this pin to VSS_RX with a 1.0μF capacitor placed as close as possible to the package. |
| B2 | VTXOUT | — | — | — | Radio Transmitter Supply Voltage Output. Bypass this pin to VSS_TX with a 1.0μF capacitor placed as close as possible to the package. |
| B8 | VBST | — | — | — | Boosted Supply Voltage for the Gate Drive of High-Side Switches. Bypass VBST to LXB with a 3.3nF capacitor. |
| B7 | VREGO_A | — | — | — | Buck Converter A Voltage Output. Bypass VREGO_A with a 22μF capacitor to VSS placed as close as possible to the VREGO_A device pin. This capacitor should be placed on the PCB trace between the VREGO_A device pin and the VDDA device pin. |
| B6 | VREGO_B | — | — | — | Buck Converter B Voltage Output. Bypass VREGO_B with a 22μF capacitor to VSS placed as close as possible to the VREGO_B device pin.This capacitor should be placed on the PCB trace between the VREGO_B device pin and the closest VCOREB device pin. |
| A6 | VREGO_C | — | — | — | Buck Converter C Voltage Output. Bypass VREGO_C with a 22μF capacitor to VSS placed as close as possible to the VREGO_C device pin. This capacitor should be placed on the PCB trace between the VREGO_C device pin and the closest VCOREA device pin. |
| A7 | VREGO_D | — | — | — | Buck Converter D Voltage Output. Bypass VREGO_D with a 22μF capacitor to VSS placed as close as possible to the VREGO_D device pin. This capacitor should be placed on the PCB trace between the VREGO_D device pin and the BLE_LDO_IN device pin. |
| J5 | VDDIO | — | — | — | GPIO Supply Voltage. Bypass this pin to VSS with a 1.0μF capacitor placed as close as possible to the package. |
| J4 | VDDIOH | — | — | — | GPIO Supply Voltage, High. VDDIOH ≥ VDDIO. Bypass this pin to VSS with a 1.0μF capacitor placed as close as possible to the package. |
| D1, E9 | VSS | — | — | — | Digital Ground |
| A5 | VSSA | — | — | — | Analog Ground |
| A9 | VSSPWR | — | — | — | Ground for the SIMO SMPS. This device pin is the return path for VREGI device pins C6 and C9. |
| C3 | VSS_RX | — | — | — | Bluetooth Receiver Ground |
| A2 | VSS_TX | — | — | — | Bluetooth Transmitter Ground |
| B9 | LXA | — | — | — | Switching Inductor Input A. Connect a 2.2μH inductor between LXA and LXB. |
| A8 | LXB | — | — | — | Switching Inductor Input B. Connect a 2.2μH inductor between LXA and LXB. |
| RESET AND CONTROL | |||||
| F6 | RSTN | — | — | — |
Active-Low, External System Reset Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. This pin has an internal pullup to the VDDIOH supply. |
| CLOCK | |||||
| A3 | 32KOUT | — | — | — | 32kHz Crystal Oscillator Output |
| A4 | 32KIN | — | — | — | 32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source. |
| C2 | HFXOUT | — | — | — | 32MHz Crystal Oscillator Output |
| C1 | HFXIN | — | — | — | 32MHz Crystal Oscillator Input. Connect a 32MHz crystal between HFXIN and HFXOUT for Bluetooth operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source. |
| GPIO AND ALTERNATE FUNCTION | |||||
| F7 | P0.0 | P0.0 | UART0A_RX | — | UART0 Receive Port Map A |
| E7 | P0.1 | P0.1 | UART0A_TX | — | UART0 Transmit Port Map A |
| F8 | P0.2 | P0.2 | TMR0A_IOA | UART0B_CTS | Timer 0 I/O 32 Bits or Lower 16 Bits Port Map A; UART0 Clear to Send Port Map B |
| F9 | P0.3 | P0.3 | EXT_CLK/TMR0A_IOB | UART0B_RTS | External Clock for Use as SYS_OSC/Timer 0 I/O Upper 16 Bits Port Map A; UART0 Request to Send Port Map B |
| G9 | P0.4 | P0.4 | SPI0_SS0 | TMR0B_IOAN | SPI0 Slave Select 0; Timer 0 Inverted Output Port Map B |
| G8 | P0.5 | P0.5 | SPI0_MOSI | TMR0B_IOBN | SP0 Master Out Slave In Serial Data 0; 32-bit Timer 0 Inverted Output Upper 16 Bits Port Map B |
| G7 | P0.6 | P0.6 | SPI0_MISO | OWM_IO | SPI0 Master In Slave Out Serial Data 1; 1-Wire Master Data I/O |
| H9 | P0.7 | P0.7 | SPI0_SCK | OWM_PE | SPI0 Clock; 1-Wire Master Pullup Enable Output |
| H8 | P0.8 | P0.8 | SPI0_SDIO2 | TMR0B_IOA | SPI0 Data 2 I/O; Timer 0 I/O 32 Bits or Lower 16 Bits Port Map B |
| J9 | P0.9 | P0.9 | SPI0_SDIO3 | TMR0B_IOB | SPI0 Data 3 I/O; Timer 0 I/O Upper 16 Bits Port Map B |
| H7 | P0.10 | P0.10 | I2C0_SCL | SPI0_SS2 | I2C0 Clock; SPI0 Slave Select 2 |
| J8 | P0.11 | P0.11 | I2C0_SDA | SPI0_SS1 | I2C0 Serial Data; SPI0 Slave Select 1 |
| G6 | P0.12 | P0.12 | UART1A_RX | TMR1B_IOAN | UART1 Receive Port Map A; Timer 1 Inverted Output Port Map B |
| H6 | P0.13 | P0.13 | UART1A_TX | TMR1B_IOBN | UART1 Transmit Port Map A; Timer 1 Inverted Output Upper 16 Bits Port Map B |
| J7 | P0.14 | P0.14 | TMR1A_IOA | UART1B_CTS | Timer 1 I/O 32 Bits or Lower 16 Bits Port Map A; UART1 Clear to Send Port Map B |
| J6 | P0.15 | P0.15 | TMR1A_IOB | UART1B_RTS | Timer 1 I/O Upper 16 Bits Port Map A; UART1 Request to Send Port Map B |
| G5 | P0.16 | P0.16 | I2C1_SCL | PT2 | I2C1 Clock; Pulse Train 2 |
| F5 | P0.17 | P0.17 | I2C1_SDA | PT3 | I2C1 Serial Data; Pulse Train 3 |
| H5 | P0.18 | P0.18 | PT0 | OWM_IO | Pulse Train 0; 1-Wire Master Data I/O |
| G4 | P0.19 | P0.19 | PT1 | OWM_PE | Pulse Train 1; 1-Wire Master Pullup Enable Output |
| H4 | P0.20 | P0.20 | SPI1_SS0 | TMR1B_IOA | SPI1 Slave Select 0; Timer 1 I/O 32 Bits or Lower 16 Bits Port Map B |
| J3 | P0.21 | P0.21 | SPI1_MOSI | TMR1B_IOB | SPI1_Master Out Slave In Serial Data 0; Timer 1 I/O Upper 16 Bits Port Map B |
| H3 | P0.22 | P0.22 | SPI1_MISO | TMR1B_IOAN | SPI1 Master In Slave Out Serial Data 1; Timer 1 Inverted Output Port Map B |
| G3 | P0.23 | P0.23 | SPI1_SCK | TMR1B_IOBN | SPI1 Clock; Timer 1 Inverted Output Upper 16 Bits Port Map B |
| J2 | P0.24 | P0.24 | SPI1_SDIO2 | TMR2B_IOA | SPI1 Data 2; Timer 2 I/O 32 Bits or Lower 16 Bits Port Map B |
| J1 | P0.25 | P0.25 | SPI1_SDIO3 | TMR2B_IOB | SPI1 Data 3; Timer 2 I/O Upper 16 Bits Port Map B |
| H1 | P0.26 | P0.26 | TMR2A_IOA | SPI1_SS1 | Timer 2 I/O 32 Bits or Lower 16 Bits Port Map A; SPI1 Slave Select 1 |
| H2 | P0.27 | P0.27 | TMR2A_IOB | SPI1_SS2 | Timer 2 I/O Upper 16 Bits Port Map A; SPI1 Slave Select 2 |
| G1 | P0.28 | P0.28 | SWDIO | — | Serial Wire Debug Data I/O |
| G2 | P0.29 | P0.29 | SWCLK | — | Serial Wire Debug Clock |
| F1 | P0.30 | P0.30 | I2C2_SCL | UART2B_CTS | I2C2 Clock; UART2 Clear to Send Port Map B |
| F4 | P0.31 | P0.31 | I2C2_SDA | UART2B_RTS | I2C2 Serial Data; UART2 Request to Send Port Map B |
| F3 | P1.0 | P1.0 | UART2A_RX | RV_TCK | UART2 Receive Port Map A; 32-Bit RISC-V Test Port Clock |
| F2 | P1.1 | P1.1 | UART2A_TX | RV_TMS | UART2 Transmit Port Map A; 32-Bit RISC-V Test Port Select |
| D5 | P1.2 | P1.2 | I2S_SCK | RV_TDI | I2S Bit Clock; 32-Bit RISC-V Test Port Data Input |
| E4 | P1.3 | P1.3 | I2S_WS | RV_TDO | I2S Left/Right Clock; 32-Bit RISC-V Test Port Data Output |
| E1 | P1.4 | P1.4 | I2S_SDI | TMR3B_IOA | I2S Serial Data Input; Timer 3 I/O 32 Bits or Lower 16 Bits Port Map B |
| E3 | P1.5 | P1.5 | I2S_SDO | TMR3B_IOB | I2S Serial Data Output; Timer 3 I/O Upper 16 Bits Port Map B |
| E2 | P1.6 | P1.6 | TMR3A_IOA | BLE_ANT_CTRL2 | Timer 3 I/O 32 Bits or Lower 16 Bits Port Map A; Bluetooth Antenna Control Line 2 |
| D4 | P1.7 | P1.7 | TMR3A_IOB | BLE_ANT_CTRL3 | Timer 3 I/O Upper 16 Bits Port Map A; Bluetooth Antenna Control Line 3 |
| D2 | P1.8 | P1.8 | BLE_ANT_CTRL0 | RXEV0 | Bluetooth Antenna Control Line 0; CM4 Rx Event Input |
| D3 | P1.9 | P1.9 | BLE_ANT_CTRL1 | TXEV0 | Bluetooth Antenna Control Line 1; CM4 Tx Event Output |
| C4 | P2.0 | P2.0 | AIN0/AIN0N | — | Analog-to-Digital Converter Input 0/Comparator 0 Negative Input |
| C5 | P2.1 | P2.1 | AIN1/AIN0P | — | Analog-to-Digital Converter Input 1/Comparator 0 Positive Input |
| D8 | P2.2 | P2.2 | AIN2/AIN1N | — | Analog-to-Digital Converter Input 2/Comparator 1 Negative Input |
| E8 | P2.3 | P2.3 | AIN3/AIN1P | — | Analog-to-Digital Converter Input 3/Comparator 1 Positive Input |
| C7 | P2.4 | P2.4 | AIN4/AIN2N | LPTMR0B_IOA | Analog-to-Digital Converter Input 4/Comparator 2 Negative Input; Low-Power Timer 0 I/O Port Map B |
| D7 | P2.5 | P2.5 | AIN5/AIN2P | LPTMR1B_IOA | Analog-to-Digital Converter Input 5/Comparator 2 Positive Input; Low-Power Timer 1 I/O Port Map B |
| C6 | P2.6 | P2.6 | LPTMR0_CLK/AIN6/AIN3N | LPUARTB_RX | Low-Power Timer 0 External Clock Input/Analog-to-Digital Converter Input 6/Comparator 3 Negative Input; Low-Power UART 0 Receive Port Map B |
| D6 | P2.7 | P2.7 | LPTMR1_CLK/AIN7/AIN3P | LPUARTB_TX | Low-Power Timer 1 External Clock Input/Analog-to-Digital Converter Input 7/Comparator 3 Positive Input; Low-Power UART Transmit Port Map B |
| E5 | P3.0 | P3.0 | PDOWN | WAKEUP | Power-Down Output; Wakeup Input. This device pin can only be powered by VDDIOH. |
| E6 | P3.1 | P3.1 | SQWOUT | WAKEUP | Square-Wave Output; Wakeup Input. This device pin can only be powered by VDDIOH. |
| ANTENNA OUTPUT | |||||
| A1 | ANT | — | — | — | Antenna for Bluetooth Radio. Attach the single-ended, unbalanced Bluetooth radio antenna. |
| PIN | NAME | FUNCTION MODE | FUNCTION | ||
| Primary Signal (Default) | Alternate Function 1 | Alternate Function 2 | |||
| POWER (See the Applications Information section for bypass capacitor recommendations.) | |||||
| F8, H4 | VREGI | — | — | — | Battery Power Supply for the SIMO Switch-Mode Power Supply (SMPS). Bypass device pin H4 with 2 x 47μF capacitors placed as close as possible to the device pin H4 and VSSPWR pins for applications using a coin cell as the battery. See Bypass Capacitors for more information. If power to the device is cycled, the voltage applied to this device pin must reach VREGI (rising). |
| H3 | BLE_LDO_IN | — | — | — | Bluetooth LDO Input. Bypass BLE_LDO_IN with a 100nF capacitor to VSS placed as close as possible to the BLE_LDO_IN device pin. |
| F5 | VDDA | — | — | — | 1.8V Analog Power Supply |
| E7 | VCOREA | — | — | — | Digital Core Supply Voltage A |
| E8 | VCOREB | — | — | — | Digital Core Supply Voltage B |
| F2 | VRXOUT | — | — | — | Radio Receiver Supply Voltage Output. Bypass this pin to VSS_RX with a 1.0μF capacitor placed as close as possible to the package. |
| G2 | VTXOUT | — | — | — | Radio Transmitter Supply Voltage Output. Bypass this pin to VSS_TX with a 1.0μF capacitor placed as close as possible to the package. |
| F7 | VBST | — | — | — | Boosted Supply Voltage for the Gate Drive of High-Side Switches. Bypass VBST to LXB with a 3.3nF capacitor. |
| G6 | VREGO_A | — | — | — | Buck Converter A Voltage Output. Bypass VREGO_A with a 22μF capacitor to VSS placed as close as possible to the VREGO_A device pin. This capacitor should be placed on the PCB trace between the VREGO_A device pin and the VDDA device pin. |
| H6 | VREGO_B | — | — | — | Buck Converter B Voltage Output. Bypass VREGO_B with a 22μF capacitor to VSS placed as close as possible to the VREGO_B device pin.This capacitor should be placed on the PCB trace between the VREGO_B device pin and the closest VCOREB device pin. |
| H5 | VREGO_C | — | — | — | Buck Converter C Voltage Output. Bypass VREGO_C with a 22μF capacitor to VSS placed as close as possible to the VREGO_C device pin. This capacitor should be placed on the PCB trace between the VREGO_C device pin and the closest VCOREA device pin. |
| G5 | VREGO_D | — | — | — | Buck Converter D Voltage Output. Bypass VREGO_D with a 22μF capacitor to VSS placed as close as possible to the VREGO_D device pin. This capacitor should be placed on the PCB trace between the VREGO_D device pin and the BLE_LDO_IN device pin. |
| D1 | VDDIO | — | — | — | GPIO Supply Voltage. Bypass this pin to VSS with a 1.0μF capacitor placed as close as possible to the package. |
| D2 | VDDIOH | — | — | — | GPIO Supply Voltage, High. VDDIOH ≥ VDDIO. Bypass this pin to VSS with a 1.0μF capacitor placed as close as possible to the package. |
| D8 | VSS | — | — | — | Digital Ground |
| F4 | VSSA | — | — | — | Analog Ground |
| G7 | VSSPWR | — | — | — | Ground for the SIMO SMPS. This device pin is the return path for VREGI device pins C6 and C9. |
| F1 | VSS_RX | — | — | — | Bluetooth Receiver Ground |
| G1 | VSS_TX | — | — | — | Bluetooth Transmitter Ground |
| G8 | LXA | — | — | — | Switching Inductor Input A. Connect a 2.2μH inductor between LXA and LXB. |
| H7 | LXB | — | — | — | Switching Inductor Input B. Connect a 2.2μH inductor between LXA and LXB. |
| RESET AND CONTROL | |||||
| B8 | RSTN | — | — | — |
Active-Low, External System Reset Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. This pin has an internal pullup to the VDDIOH supply. |
| CLOCK | |||||
| G3 | 32KOUT | — | — | — | 32kHz Crystal Oscillator Output |
| G4 | 32KIN | — | — | — | 32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source. |
| E1 | HFXOUT | — | — | — | 32MHz Crystal Oscillator Output |
| E2 | HFXIN | — | — | — | 32MHz Crystal Oscillator Input. Connect a 32MHz crystal between HFXIN and HFXOUT for Bluetooth operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source. |
| GPIO AND ALTERNATE FUNCTION (See the Applications Information section for GPIO and Alternate Function Matrices.) | |||||
| C8 | P0.2 | P0.2 | TMR0A_IOA | UART0B_CTS | Timer 0 I/O 32 Bits or Lower 16 Bits Port Map A; UART0 Clear to Send Port Map B |
| D7 | P0.3 | P0.3 | EXT_CLK/TMR0A_IOB | UART0B_RTS | External Clock for Use as SYS_OSC/Timer 0 I/O Upper 16 Bits Port Map A; UART0 Request to Send Port Map B |
| C7 | P0.4 | P0.4 | SPI0_SS0 | TMR0B_IOAN | SPI0 Slave Select 0; Timer 0 Inverted Output Port Map B |
| B7 | P0.5 | P0.5 | SPI0_MOSI | TMR0B_IOBN | SP0 Master Out Slave In Serial Data 0; 32-Bit Timer 0 Inverted Output Upper 16 Bits Port Map B |
| A7 | P0.6 | P0.6 | SPI0_MISO | OWM_IO | SPI0 Master In Slave Out Serial Data 1; 1-Wire Master Data I/O |
| D6 | P0.7 | P0.7 | SPI0_SCK | OWM_PE | SPI0 Clock; 1-Wire Master Pullup Enable Output |
| C6 | P0.8 | P0.8 | SPI0_SDIO2 | TMR0B_IOA | SPI0 Data 2 I/O; Timer 0 I/O 32 Bits or Lower 16 Bits Port Map B |
| B6 | P0.9 | P0.9 | SPI0_SDIO3 | TMR0B_IOB | SPI0 Data 3 I/O; Timer 0 I/O Upper 16 Bits Port Map B |
| A6 | P0.10 | P0.10 | I2C0_SCL | SPI0_SS2 | I2C0 Clock; SPI0 Slave Select 2 |
| E5 | P0.11 | P0.11 | I2C0_SDA | SPI0_SS1 | I2C0 Serial Data; SPI0 Slave Select 1 |
| D5 | P0.12 | P0.12 | UART1A_RX | TMR1B_IOAN | UART1 Receive Port Map A; Timer 1 Inverted Output Port Map B |
| C5 | P0.13 | P0.13 | UART1A_TX | TMR1B_IOBN | UART1 Transmit Port Map A; Timer 1 Inverted Output Upper 16 Bits Port Map B |
| A5 | P0.14 | P0.14 | TMR1A_IOA | UART1B_CTS | Timer 1 I/O 32 Bits or Lower 16 Bits Port Map A; UART1 Clear to Send Port Map B |
| B5 | P0.15 | P0.15 | TMR1A_IOB | UART1B_RTS | Timer 1 I/O Upper 16 Bits Port Map A; UART1 Request to Send Port Map B |
| D4 | P0.18 | P0.18 | PT0 | OWM_IO | Pulse Train 0; 1-Wire Master Data I/O |
| A4 | P0.19 | P0.19 | PT1 | OWM_PE | Pulse Train 1; 1-Wire Master Pullup Enable Output |
| B4 | P0.26 | P0.26 | TMR2A_IOA | SPI1_SS1 | Timer 2 I/O 32 Bits or Lower 16 Bits Port Map A; SPI1 Slave Select 1 |
| C4 | P0.27 | P0.27 | TMR2A_IOB | SPI1_SS2 | Timer 2 I/O Upper 16 Bits Port Map A; SPI1 Slave Select 2 |
| A2 | P0.28 | P0.28 | SWDIO | — | Serial Wire Debug Data I/O |
| A3 | P0.29 | P0.29 | SWCLK | — | Serial Wire Debug Clock |
| B3 | P1.0 | P1.0 | UART2A_RX | RV_TCK | UART2 Receive Port Map A; 32-Bit RISC-V Test Port Clock |
| C3 | P1.1 | P1.1 | UART2A_TX | RV_TMS | UART2 Transmit Port Map A; 32-Bit RISC-V Test Port Select |
| B2 | P1.2 | P1.2 | I2S_SCK | RV_TDI | I2S Bit Clock; 32-Bit RISC-V Test Port Data Input |
| B1 | P1.3 | P1.3 | I2S_WS | RV_TDO | I2S Left/Right Clock; 32-Bit RISC-V Test Port Data Output |
| E4 | P1.4 | P1.4 | I2S_SDI | TMR3B_IOA | I2S Serial Data Input; Timer 3 I/O 32 Bits or Lower 16 Bits Port Map B |
| D3 | P1.5 | P1.5 | I2S_SDO | TMR3B_IOB | I2S Serial Data Output; Timer 3 I/O Upper 16 Bits Port Map B |
| C2 | P1.6 | P1.6 | TMR3A_IOA | BLE_ANT_CTRL2 | Timer 3 I/O 32 Bits or Lower 16 Bits Port Map A; Bluetooth Antenna Control Line 2 |
| C1 | P1.7 | P1.7 | TMR3A_IOB | BLE_ANT_CTRL3 | Timer 3 I/O Upper 16 Bits Port Map A; Bluetooth Antenna Control Line 3 |
| F3 | P1.8 | P1.8 | BLE_ANT_CTRL0 | RXEV0 | Bluetooth Antenna Control Line 0; CM4 Rx Event Input |
| E3 | P1.9 | P1.9 | BLE_ANT_CTRL1 | TXEV0 | Bluetooth Antenna Control Line 1; CM4 Tx Event Output |
| E6 | P3.0 | P3.0 | PDOWN | WAKEUP | Power-Down Output; Wakeup Input. This device pin can only be powered by VDDIOH. |
| F6 | P3.1 | P3.1 | SQWOUT | WAKEUP | Square-Wave Output; Wakeup Input. This device pin can only be powered by VDDIOH. |
| ANTENNA OUTPUT | |||||
| H2 | ANT | — | — | — | Antenna for Bluetooth Radio. Attach the single-ended, unbalanced Bluetooth radio antenna. |