| Package Code | X8188+4C |
| Outline Number | 21-0735 |
| Land Pattern Number | 90-0460 |
| Thermal Resistance, Four-Layer Board: | |
| Junction to Ambient (θJA) | 41.49°C/W |
| Junction to Case (θJC) | 10.81°C/W |
| Package Code | W603B3+1 |
| Outline Number | 21-100635 |
| Land Pattern Number | Refer to Application Note 1891 |
| Thermal Resistance, Four-Layer Board: | |
| Junction to Ambient (θJA) | 44.78°C/W |
| Junction to Case (θJC) | N/A |
data-opMAX32655GXG%2B
data-opMAX32655GXG%2BT
Battery Power Supply for the SIMO Switch-Mode Power Supply (SMPS). Bypass device pin H4 with 2 x 47μF capacitors placed as close as possible to the device pin H4 and VSSPWR pins for applications using a coin cell as the battery. See Bypass Capacitors for more information. If power to the device is cycled, the voltage applied to this device pin must reach VREGI (rising).Bluetooth LDO Input. Bypass BLE_LDO_IN with a 100nF capacitor to VSS placed as close as possible to the BLE_LDO_IN device pin.1.8V Analog Power SupplyDigital Core Supply Voltage ADigital Core Supply Voltage BRadio Receiver Supply Voltage Output. Bypass this pin to VSS_RX with a 1.0μF capacitor placed as close as possible to the package.Radio Transmitter Supply Voltage Output. Bypass this pin to VSS_TX with a 1.0μF capacitor placed as close as possible to the package.Boosted Supply Voltage for the Gate Drive of High-Side Switches. Bypass VBST to LXB with a 3.3nF capacitor.Buck Converter A Voltage Output. Bypass VREGO_A with a 22μF capacitor to VSS placed as close as possible to the VREGO_A device pin. This capacitor should be placed on the PCB trace between the VREGO_A device pin and the VDDA device pin.Buck Converter B Voltage Output. Bypass VREGO_B with a 22μF capacitor to VSS placed as close as possible to the VREGO_B device pin.This capacitor should be placed on the PCB trace between the VREGO_B device pin and the closest VCOREB device pin.Buck Converter C Voltage Output. Bypass VREGO_C with a 22μF capacitor to VSS placed as close as possible to the VREGO_C device pin. This capacitor should be placed on the PCB trace between the VREGO_C device pin and the closest VCOREA device pin.Buck Converter D Voltage Output. Bypass VREGO_D with a 22μF capacitor to VSS placed as close as possible to the VREGO_D device pin. This capacitor should be placed on the PCB trace between the VREGO_D device pin and the BLE_LDO_IN device pin.GPIO Supply Voltage. Bypass this pin to VSS with a 1.0μF capacitor placed as close as possible to the package.GPIO Supply Voltage, High. VDDIOH ≥ VDDIO. Bypass this pin to VSS with a 1.0μF capacitor placed as close as possible to the package.Digital GroundAnalog GroundGround for the SIMO SMPS. This device pin is the return path for VREGI device pins C6 and C9.Bluetooth Receiver GroundBluetooth Transmitter GroundSwitching Inductor Input A. Connect a 2.2μH inductor between LXA and LXB.Switching Inductor Input B. Connect a 2.2μH inductor between LXA and LXB.Active-Low, External System Reset Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR (resetting all logic on all supplies except for real-time clock circuitry) and begins execution.
This pin has an internal pullup to the VDDIOH supply.32kHz Crystal Oscillator Output32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source.32MHz Crystal Oscillator Output32MHz Crystal Oscillator Input. Connect a 32MHz crystal between HFXIN and HFXOUT for Bluetooth operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source.UART0 Receive Port Map AUART0 Transmit Port Map ATimer 0 I/O 32 Bits or Lower 16 Bits Port Map A; UART0 Clear to Send Port Map BExternal Clock for Use as SYS_OSC/Timer 0 I/O Upper 16 Bits Port Map A; UART0 Request to Send Port Map BSPI0 Slave Select 0; Timer 0 Inverted Output Port Map BSP0 Master Out Slave In Serial Data 0; 32-Bit Timer 0 Inverted Output Upper 16 Bits Port Map BSPI0 Master In Slave Out Serial Data 1; 1-Wire Master Data I/OSPI0 Clock; 1-Wire Master Pullup Enable OutputSPI0 Data 2 I/O; Timer 0 I/O 32 Bits or Lower 16 Bits Port Map BSPI0 Data 3 I/O; Timer 0 I/O Upper 16 Bits Port Map BI2C0 Clock; SPI0 Slave Select 2I2C0 Serial Data; SPI0 Slave Select 1UART1 Receive Port Map A; Timer 1 Inverted Output Port Map BUART1 Transmit Port Map A; Timer 1 Inverted Output Upper 16 Bits Port Map BTimer 1 I/O 32 Bits or Lower 16 Bits Port Map A; UART1 Clear to Send Port Map BTimer 1 I/O Upper 16 Bits Port Map A; UART1 Request to Send Port Map BI2C1 Clock; Pulse Train 2I2C1 Serial Data; Pulse Train 3Pulse Train 0; 1-Wire Master Data I/OPulse Train 1; 1-Wire Master Pullup Enable OutputSPI1 Slave Select 0; Timer 1 I/O 32 Bits or Lower 16 Bits Port Map BSPI1_Master Out Slave In Serial Data 0; Timer 1 I/O Upper 16 Bits Port Map BSPI1 Master In Slave Out Serial Data 1; Timer 1 Inverted Output Port Map B SPI1 Clock; Timer 1 Inverted Output Upper 16 Bits Port Map BSPI1 Data 2; Timer 2 I/O 32 Bits or Lower 16 Bits Port Map BSPI1 Data 3; Timer 2 I/O Upper 16 Bits Port Map BTimer 2 I/O 32 Bits or Lower 16 Bits Port Map A; SPI1 Slave Select 1Timer 2 I/O Upper 16 Bits Port Map A; SPI1 Slave Select 2Serial Wire Debug Data I/OSerial Wire Debug ClockI2C2 Clock; UART2 Clear to Send Port Map BI2C2 Serial Data; UART2 Request to Send Port Map BUART2 Receive Port Map A; 32-Bit RISC-V Test Port ClockUART2 Transmit Port Map A; 32-Bit RISC-V Test Port SelectI2S Bit Clock; 32-Bit RISC-V Test Port Data InputI2S Left/Right Clock; 32-Bit RISC-V Test Port Data OutputI2S Serial Data Input; Timer 3 I/O 32 Bits or Lower 16 Bits Port Map BI2S Serial Data Output; Timer 3 I/O Upper 16 Bits Port Map BTimer 3 I/O 32 Bits or Lower 16 Bits Port Map A; Bluetooth Antenna Control Line 2Timer 3 I/O Upper 16 Bits Port Map A; Bluetooth Antenna Control Line 3Bluetooth Antenna Control Line 0; CM4 Rx Event InputBluetooth Antenna Control Line 1; CM4 Tx Event OutputAnalog-to-Digital Converter Input 0/Comparator 0 Negative InputAnalog-to-Digital Converter Input 1/Comparator 0 Positive InputAnalog-to-Digital Converter Input 2/Comparator 1 Negative InputAnalog-to-Digital Converter Input 3/Comparator 1 Positive InputAnalog-to-Digital Converter Input 4/Comparator 2 Negative Input; Low-Power Timer 0 I/O Port Map BAnalog-to-Digital Converter Input 5/Comparator 2 Positive Input; Low-Power Timer 1 I/O Port Map BLow-Power Timer 0 External Clock Input/Analog-to-Digital Converter Input 6/Comparator 3 Negative Input; Low-Power UART 0 Receive Port Map BLow-Power Timer 1 External Clock Input/Analog-to-Digital Converter Input 7/Comparator 3 Positive Input; Low-Power UART Transmit Port Map BPower-Down Output; Wakeup Input. This device pin can only be powered by VDDIOH.Square-Wave Output; Wakeup Input. This device pin can only be powered by VDDIOH.Antenna for Bluetooth Radio. Attach the single-ended, unbalanced Bluetooth radio antenna.