Detailed Description

The Arm Cortex-M4 with FPU processor is ideal for low-power system control. The architecture combines high-efficiency signal processing functionality with low power, low cost, and ease of use.

The Arm Cortex-M4 with FPU DSP supports single instruction multiple data (SIMD) path DSP extensions, providing:

• Four parallel 8-bit add/sub
• Floating-point single precision
• Two parallel 16-bit add/sub
• Two parallel MACs
• 32- or 64-bit accumulate
• Signed and unsigned data with or without saturation

The addition of 32-bit RISC-V processor (RV32) provides the system with ultra-low-power consumption signal processing.

Bluetooth 5.2 LE is the latest version of the Bluetooth wireless communication standard. It is used for wireless headphones and other audio hardware, as well as for communication between various smart home and internet of things (IoT) devices. Bluetooth LE communications operate in the unlicensed 2.4GHz industrial-scientific-medical (ISM) band. A frequency-hopping transceiver is used to combat interference and fading. The system operates in the 2.4GHz ISM band at 2400MHz to 2483.5MHz. It uses 40 RF channels. These RF channels have center frequencies 2402 + k x 2MHz, where k = 0, ..., 39. The Bluetooth stack runs on RV32 so that the CM4 can be freed to run application code. The features of the radio include the following:

• Higher transmit power up to +4.5dbm
• 1Mbps, 2Mbps, and long-range coded (125kbps and 500kbps)
• Increased broadcast capability
  • Advertising packet up to 255 bytes
• On-chip matching network to the antenna
• Antenna control outputs
• Direction finding with AoA and AoD
• Provides hardware on-the-fly encryption and decryption for lower power consumption
• Low transmit current of 4.17mA at 0dbm at 3.3V
• Low receive current of 4.0mA at 3.3V
• Supports mesh networking
• Supports high-quality audio streaming (isochronous)

A Bluetooth 5.2 software stack is available for application developers to quickly add support to devices. The Arm Cordio^®-B50 software stack is provided in library form and provides application developers access to Bluetooth technology without validation and development of a software stack. The Cordio-B50 software stack interfaces to the Bluetooth link layer running on dedicated hardware. The dedicated hardware for the stack enables the ultimate in power management for IoT applications. Cordio-B50 features the following:

• C library for linking directly into an application development tool
• Change PHY support
  • Host selects the PHY it needs to use at any given time enabling long range or higher bandwidth only when required
    • Bluetooth LE 1M
    • Bluetooth LE Coded S = 2
    • Bluetooth LE Coded S = 8
    • Bluetooth LE 2M
• Bluetooth 5.2 advertising extension support for enabling next-generation Bluetooth beacons
  • Larger packets and advertising channel offloading
  • Packets up to 255 octets long
  • Advertising packet chaining
  • Advertising sets
  • Periodic advertising
  • High-duty cycle non-connectable advertising
  • Sample applications using standard profiles built on the Cordio-B50 software framework

The eight AIN[7:0] inputs can be configured as four pairs and deployed as four independent comparators with the following features:

• Comparison events can trigger interrupts
• Events can wake the CM4 from SLEEP, LOW POWER, MICRO POWER, STANDBY, or BACKUP operating modes
• Can be active in all power modes

See Table 1 for details of instances of the comparators.

The DVS controller works using the fixed high-speed oscillator and the V_COREA supply  voltage to optimally operate the Arm core at the lowest practical voltage. The ability to adaptively adjust the voltage provides a significant reduction in dynamic power consumption.

The DVS controller provides the following features:

• DVS monitoring and adjustment functions
• Continuous monitoring with programmable monitor sample period
• Controlled transition to a programmable operating point
• Independent high and low operating limits for safe, bounded operation
• Independent high, center, and low operating range delay line monitors
• Programmable adjustment rate when an adjustment is required
• Single clock operation
• APB interface provides IP control and status access
• Interrupt capability during error

Multiple clock sources can be selected as the system clock:

• Internal primary oscillator (IPO) at a nominal frequency of 100MHz
• Internal secondary oscillator (ISO) at a nominal frequency of 60MHz
• Configurable internal nano-ring oscillator (INRO) at 8kHz, 16kHz, or 30kHz
• External RTC oscillator at 32.768kHz (ERTCO)—external crystal required
• Internal baud rate oscillator at 7.3728MHz (IBRO)
• External square-wave clock up to 80MHz
• External RF oscillator at 32MHz (ERFO)—external crystal required

There are multiple external clock inputs:

• LPTMR0 and LPTMR1 can be clocked from unique external sources (81 CTBGA only).
• SYS_CLK can be derived from an external source.

Most GPIO pins share both a firmware-controlled I/O function and one or more alternate functions associated with peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a special function usually supersedes its use as a firmware-controlled I/O. Although this multiplexing between peripheral and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are identical whether the pin is configured as an I/O or special function, except where explicitly noted in the Electrical Characteristics tables.

In GPIO mode, pins are logically divided into ports of 32 pins. Each pin of a port has an interrupt function that can be independently enabled, and configured as a level- or edge-sensitive interrupt. All GPIOs of a given port share the same interrupt vector.

When configured as GPIO, all features can be independently enabled or disabled on a per-pin basis. The following features are provided:

• Configurable as input, output, bidirectional, or high impedance
• Optional internal pullup resistor or internal pulldown resistor when configured as input
• Exit from low-power modes on rising or falling edge
• Selectable standard- or high-drive modes

The MAX32655 provides up to 52 GPIO pins. Caution is needed since Port 3 (P3.0 and P3.1 device pins) is configured in a different manner from the above description.

The 10-bit sigma-delta (Σ-Δ) ADC provides an integrated reference generator and a single-ended input multiplexer. The multiplexer selects an input channel from one of the eight external analog input signals (AIN0–AIN7) or the internal power supply inputs.

The reference for the ADC can be:

• Internal 1.22V bandgap
• V_SSA analog supply

An optional feature allows samples captured by the ADC to be automatically compared against user-programmable high and low limits. Up to four channel limit pairs can be configured in this way. The comparison allows the ADC to trigger an interrupt (and potentially wake the CPU from a power mode) when a captured sample goes outside the preprogrammed limit range. Since this comparison is performed directly by the sample limit monitors, it can be performed even while the CPU is in SLEEP, LOW POWER or MICRO POWER mode. The eight AIN[7:0] inputs can be configured as four pairs and deployed as four independent comparators.

​The ADC measures the following voltages:

• AIN[7:0] up to 3.3V
• V_REGI
• V_COREA
• V_COREB
• V_DDIOH
• V_DDIO
• V_TXOUT
• V_RXOUT
• V_DDA

See Table 2 for details of instances of the ADC.

The PMU provides high-performance operation while minimizing power consumption. It exercises intelligent, precise control of power distribution to the CPUs and peripheral circuitry.

The PMU provides the following features:

• User-configurable system clock
• Automatic enabling and disabling of crystal oscillators based on power mode
• Multiple power domains
• Fast wake-up of powered-down peripherals when activity detected

This mode consumes less power, but wakes faster because the clocks can optionally be enabled.

The device status is as follows:

• CM4 is asleep
• RV32 is asleep
• Peripherals are on
• Standard DMA is available for optional use

This mode is suitable for running the RV32 processor to collect and move data from enabled peripherals.

The device status is a follows:

• The CM4, SRAM0, and SRAM1 are in state retention.
• The RV32 can access the SPI, all UARTS, all timers, I²C, 1-Wire, pulse train engines, I²S, CRC, AES, TRNG, PCIF, and comparators, as well as SRAM2 and SRAM3. SRAM3 can be configured to operate as RV32 instruction cache
• The transition from LOW POWER mode to ACTIVE mode is faster than the transition from BACKUP mode because system initialization is not required.
• The DMA can access flash.
• IPO can be optionally powered down.
• The following oscillators are enabled:
  • IBRO
  • ERTCO
  • INRO
  • ISO
  • ERFO

This mode is used for extremely low power consumption while using a minimal set of peripherals to provide wakeup capability.

The device status is a follows:

• Both CM4 and RV32 are state retained. (System state and all SRAM is retained.)
• The GPIO pins retain their state.
• All non-MICRO POWER peripherals are state retained.
• IBRO can be optionally powered down.
• The following oscillators are powered down:
  • IPO
  • ISO
  • ERFO
• The following oscillators are enabled:
  • IBRO
  • ERTCO
  • INRO
• The following MICRO POWER mode peripherals are available for use to wake up the device:
  • LPUART0, LPUART1
  • WWDT1
  • All four low-power analog comparators

This mode is used to maintain the system operation while keeping time with the RTC.

The device status is as follows:

• Both CM4 and RV32 are state retained. (System state and all SRAM is retained.)
• The GPIO pins retain their state.
• RTC is on.
• All peripherals are state retained.
• The following oscillators are powered down:
  • IPO
  • ISO
  • IBRO
  • ERFO
• The following oscillators are enabled:
  • ERTCO
  • INRO

This mode is used maintain the system RAM. The device status is as follows:

• CM4 and RV32 are powered off.
• SRAM0, SRAM1, SRAM2 and SRAM3 can be configured to be state retained as per Table 3.
• All peripherals are powered off.

• The GPIO pins retain their state.
• RTC is on.
• The following oscillators are powered down:
  • IPO
  • ISO
  • IBRO
  • INRO
  • ERFO
• The following oscillators are enabled:
  • ERTCO

This mode is used during product level distribution and storage.

The device status is as follows:

• The CM4 and RV32 are powered off.
• All peripherals and SRAM are powered down.
• All oscillators are powered down.
• 8 bytes of data are retained.
• Values in the flash are preserved.
• Voltage monitors are operational.

The sources of wake-up from the SLEEP, LOW POWER, MICRO POWER, STANDBY, BACKUP, and POWER DOWN operating modes are summarized in Table 4.

An RTC keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by application software.

The RTC provides a time-of-day alarm that is programmable to any future value between 1 second and 12 days. When configured for long intervals, the time-of-day alarm is usable as a power-saving timer, allowing the device to remain in an extremely low-power mode, but still awaken periodically to perform assigned tasks. A second independent 32-bit 1/4096 subsecond alarm is programmable with a tick resolution of 244μs. Both can be configured as recurring alarms. When enabled, either alarm can cause an interrupt or wake the device from most low-power modes.

The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing requirements in the Electrical Characteristics table.

The RTC calibration feature provides the ability for user software to compensate for minor variations in the RTC oscillator, crystal, temperature, and board layout. Enabling the SQWOUT alternate function outputs a timing signal derived from the RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with 1ppm resolution. Under most circumstances, the oscillator does not require any calibration.

General-purpose, 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals with minimal software interaction.

The timer provides the following features:

• 32-bit up/down autoreload
• Programmable prescaler
• PWM output generation
• Capture, compare, and capture/compare capability
• External pin multiplexed with GPIO for timer input, clock gating, or capture
• Timer output pin
• TMR0–TMR3 can be configured as two 16-bit general-purpose timers
• Timer interrupt

The MAX32655 provides six 32-bit timers (TMR0, TMR1, TMR2, TMR3, LPTMR0, and LPTMR1). LPTMR0 and LPTMR1 are capable of operation in the SLEEP, LOW POWER, and MICRO POWER modes.

I/O functionality is supported for all of the timers. Note that the function of a port can be multiplexed with other functions on the GPIO pins, so it might not be possible to use all the ports depending on the device configuration. See Table 5 for individual timer features.

* Available as an internal timer only on the 60-WLP package. There is no external connection to this timer on the 60 WLP package.

Microcontrollers are often used in harsh environments where electrical noise and electromagnetic interference (EMI) are abundant. Without proper safeguards, these hazards can disturb device operation and corrupt program execution. One of the most effective countermeasures is the windowed WDT, which detects runaway code or system unresponsiveness.

The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically reset by the application software. Failure to reset the WDT within the user-configurable timeout period indicates that the application software is not operating correctly and results in a WDT timeout. A WDT timeout can trigger an interrupt, system reset, or both. Either response forces the instruction pointer to a known good location before resuming instruction execution. The windowed timeout period feature provides more detailed monitoring of system operation, requiring the WDT to be reset within a specific window of time. See Table 6 for individual timer features.

The MAX32655 provides two instances of the watchdog timer—WDT0 and LPWDT0.

Multiple, independent pulse train generators can provide either a square-wave or a repeating pattern from 2 to 32 bits in length. Any single pulse train generator or any desired group of pulse train generators can be synchronized at the bit level allowing for multibit patterns. Each pulse train generator is independently configurable.

The pulse train generators provide the following features:

• Independently enabled
• Safe enable and disable for pulse trains without bit banding
• Multiple pin configurations allow for flexible layout
• Pulse trains can be started/synchronized independently or as a group
• Frequency of each enabled pulse train generator is also set separately, based on a divide down (divide by 2, divide by 4, divide by 8, and so on) of the input pulse train module clock
• Input pulse train module clock can be optionally configured to be independent from the system AHB clock
• Multiple repetition options
  • Single shot (nonrepeating pattern of 2 to 32 bits)
  • Pattern repeats a user-configurable number of times or indefinitely
  • Termination of one pulse train loop count can restart one or more other pulse trains

The pulse train engine feature is an alternate function associated with a GPIO pin. In most cases, enabling the pulse train engine function supersedes the GPIO function.

See Table 7 for details of instances of the pulse train peripheral.

The I²C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can operate as a one-to-one, one-to-many, or many-to-many communications medium. This interface supports standard-mode, fast-mode, fast-mode plus, and high-speed mode I²C speeds. It provides the following features:

• Master or slave mode operation
  • Supports up to 4 different slave addresses in slave mode
• Supports standard 7-bit addressing or 10-bit addressing
• RESTART condition
• Interactive receive mode (IRXM)
• Transmitter FIFO preloading
• Support for clock stretching to allow slower slave devices to operate on higher speed busses
• Multiple transfer rates
  • Standard mode: 100kbps
  • Fast mode: 400kbps
  • Fast mode plus: 1000kbps
  • High-speed mode: 3.4Mbps
• Internal filter to reject noise spikes
• Receiver FIFO depth of 8 bytes
• Transmitter FIFO depth of 8 bytes

See Table 8 for details of the instances of the I²C peripheral.

The I²S interface is a bidirectional, four-wire serial bus that provides serial communications for codecs and audio amplifiers compliant with the I²S Bus Specification, June 5, 1996. It provides the following features:

• Master and slave mode operation
• Support for 4 channels
• 8, 16, 24, and 32-bit frames
• Receive and transmit DMA support
• Wake-up on FIFO status (full/empty/threshold)
• Pulse density modulation support for the receive channel
• Word-select polarity control
• First-bit position selection
• Interrupts generated for FIFO status​
• Receiver FIFO depth of 32 bytes
• Transmitter FIFO depth of 32 bytes

The MAX32655 provides one instance of the I²S peripheral (I2S0).

The SPI is a highly configurable, flexible, and efficient synchronous interface where multiple SPI devices can coexist on a single bus. The bus uses a single clock signal and multiple data signals, as well as one or more slave select lines to address only the intended target device. The SPI operates independently and requires minimal processor overhead.

The provided SPI peripherals can operate in either slave or master mode and provide the following features:

• SPI modes 0, 1, 2, or 3 for single-bit communication
• 3- or 4-wire mode for single-bit slave device communication
• Full-duplex operation in single-bit, 4-wire mode
• Dual and quad data modes supported
• Multiple slave selects on some instances
• Multimaster mode fault detection
• Programmable interface timing
• Programmable SCK frequency and duty cycle
• 32-byte transmit and receive FIFOs
• Slave select assertion and deassertion timing with respect to leading/trailing SCK edge

See Table 9 for SPI configuration options.

​

The universal asynchronous receiver-transmitter (UART, LPUART) interface supports full-duplex asynchronous communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a given port, the system uses two extra pins to implement the industry-standard request to send (RTS) and clear to send (CTS) flow control signaling. Each instance is individually programmable.

• 2-wire interface or 4-wire interface with flow control
• 8-byte send/receive FIFO
• Full-duplex operation for asynchronous data transfers
• Interrupts available for frame error, parity error, CTS, Rx FIFO overrun, and FIFO full/partially full conditions
• Automatic parity and frame error detection
• Independent baud-rate generator
• Programmable 9th-bit parity support
• Multidrop support
• Start/stop bit support
• Hardware flow control using RTS/CTS
• 12.5Mbps for UART maximum baud rate
• 1.85Mbps for LPUART maximum baud rate
• Two DMA channels can be connected (read and write FIFOs)
• Programmable word size (5 bits to 8 bits)

The MAX32655 provides four instances of the UART peripheral—UART0, UART1, UART2, and LPUART0. LPUART0 is capable of operation in the SLEEP, LOW POWER, and MICRO POWER modes. See Table 10 for configuration options.

Maxim's 1-Wire bus consists of one signal that carries data and also supplies power to the slave devices and a ground return. The bus master communicates serially with one or more slave devices through the bidirectional, multidrop 1-Wire bus. The single-contact serial interface is ideal for communication networks requiring minimal interconnection.

The provided 1-Wire master supports the following features:

• Single contact for control and operation
• Unique factory identifier for any 1-Wire device
• Multiple device capability on a single line

The OWM supports both standard (15.6kbps) and overdrive (110kbps) speeds.

The standard DMA controller allows automatic one-way data transfer between two entities. These entities can be either memories or peripherals. The transfers are done without using CPU resources. The following transfer modes are supported:

• 4-channel
• Peripheral to data memory
• Data memory to peripheral
• Data memory to data memory
• Event support

All DMA transactions consist of an AHB burst read into the DMA FIFO, followed immediately by an AHB burst write from the FIFO.

The MAX32655 provides one instance of the standard DMA controller.

The dedicated hardware-based AES engine supports the following algorithms:

• AES-128
• AES-192
• AES-256

The AES keys are automatically generated by the engine and stored in dedicated flash to protect against tampering. Key generation and storage is transparent to the user.

The device provides a non-deterministic entropy source that can be used to generate cryptographic seeds or strong encryption keys as part of an overall framework for a secure customer application.

Software can use random numbers to trigger asynchronous events that add complexity to program execution to thwart replay attacks or key search methodologies.

The TRNG can support the system-level validation of many security standards. Maxim Integrated will work directly with the customer’s validation laboratory to provide the laboratory with any required information. Contact Maxim Integrated for details of compliance with specific standards.

A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application software. It supports a user-defined programmable polynomial up to 32-bits. Direct memory access copies data into the CRC module so that CRC calculations on large blocks of memory are performed with minimal CPU intervention. Examples of common polynomials are depicted in Table 11.