| Package Code | T3255+8C |
| Outline Number | 21-0140 |
| Land Pattern Number | 90-0013 |
| Thermal Resistance, Single-Layer Board: | |
| Junction to Ambient (θJA) | 47°C/W |
| Junction to Case (θJC) | 1.70°C/W |
| Thermal Resistance, Four-Layer Board: | |
| Junction to Ambient (θJA) | 29°C/W |
| Junction to Case (θJC) | 1.70°C/W |
| Package Code | W302N2+1 |
| Outline Number | 21-100380 |
| Land Pattern Number | Refer to Application Note 1891 |
| Thermal Resistance, Four-Layer Board: | |
| Junction to Ambient (θJA) | 49.38°C/W |
| Junction to Case (θJC) | N/A |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.data-opMAX32520-BNJ%2B
data-opMAX32520-BNS%2B
data-opMAX32520-BNS%2BT
P0.0: GPIO0 Port 0
UART_RXD: UART Data InputP0.1: GPIO1 Port 0
UART_TXD: UART Data OutputP0.2: GPIO2 Port 0
SPI0_DIO0: Quad SPI I/O 0 (SPI0 Master Out Slave In)
SFSPIS_DIO0: Serial Flash SPI Slave I/O 0 (SFSPI Slave In)P0.3: GPIO3 Port 0
SPI0_DIO1: Quad SPI I/O 1 (SPI0 Master In Slave Out)
SFSPIS_DIO1: Serial Flash SPI I/O 1 (SFSPI Slave Out)P0.4: GPIO4 Port 0
SCK0: SPI0 Clock
SFSPIS_SCK: Serial SPI ClockP0.5: GPIO5 Port 0
SSEL0_0: SPI0 Slave Select 0
SFSPIS_SS0: Serial Flash SPI Slave Select 0P0.6: GPIO6 Port 0
SSEL0_1: SPI0 Slave Select 1
SFSPIS_SS1: Serial Flash SPI Slave Select 1P0.7: GPIO7 Port 0
SPI0_DIO2: Quad SPI I/O 2
SFSPIS_DIO2: Serial Flash SPI I/O 2P0.8: GPIO8 Port 0
SPI0_DIO3: Quad SPI I/O3
SFSPIS_DIO3: Serial Flash SPI I/O 3P0.11: GPIO11 Port 0
MISO1: SPI1 Master In Slave OutP0.12: GPIO12 Port 0
MOSI1: SPI1 Master Out Slave InP0.13: GPIO13 Port 0
SCK1: SPI1 ClockP0.14: GPIO14 Port 0
SSEL1_0: SPI1 Slave Select 0P0.15: GPIO15 Port 0
SSEL1_1: SPI1 Slave Select 1P0.9: GPIO9 Port 0
SDA: I2C DataP0.10: GPIO10 Port 0
SCL: I2C ClockP1.0: GPIO0 Port1
TCLK0: Timer 0 Clock I/OP1.1: GPIO1 Port1
TCLK1: Timer 1 Clock I/OP1.6: GPIO6 Port 1
TCLK2: Timer 2 Clock I/O
SSEL1_2: SPI1 Slave Select 2P1.7: GPIO7 Port 1
TCLK3: Timer 3 Clock I/O
SSEL1_3: SPI1 Slave Select 3P1.2: GPIO2 Port 1
TDI: JTAG Test Data InputP1.3: GPIO3 Port 1
TDO: JTAG Test Data OutputP1.4: GPIO4 Port 1
TMS/SWDIO: JTAG Mode Select / Single Wire Debug I/OP1.5: GPIO5 Port 1
TCK/SWCLK: JTAG Test Clock / Single Wire Debug ClockP1.8: GPIO8 Port 1
EXT_SENS_OUT: External Sensor OutputP1.9: GPIO9 Port 1
EXT_SENS_IN: External Sensor InputP1.10: GPIO10 Port 1
TAMPER_OUT: External Tamper Detection Output. This pin is active when external tamper is detected.VDD: Core and I/O Supply Voltage. Bypass VDD with 1μf and 100nF capacitors with ESR < 100mΩ.REG: Regulator Capacitor. Bypass REG with 1μf and 100nF capacitors with ESR < 100mΩ.VSSA: 1.8V Analog GroundVDDA: 1.8V Analog Power Supply. Bypass VDDA with 1μf and 100nF capacitors with ESR < 100mΩ.Exposed Pad. Ground.RSTN: Hardware Reset (Active-Low) Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a warm reset (resetting all logic) and begins execution. This pin has an internal pullup to the VDD supply. This pin should be left unconnected if the system design does not provide a reset signal to the device.Ground