Package Information

WLP

Package Code	N61A1+1
Outline Number	21-100395
Land Pattern Number	N/A
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ_JA)	95.15°C/W
Junction to Case (θ_JC)	N/A

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

data-opMAX31825ANT%2B

data-opMAX31825ANT%2BT

Data In/OutExternal Parasite Power Capacitor and VDD Input. Connect a 3.3nF capacitor between this pin and GND for parasite power operation. Connect power supply voltage to this pin when powering from an external VDD source.GroundAddress Selection Input. Connect to GND or VDD (DQ in parasite mode) to select the location address.Address Selection Input. Connect a resistor to GND to select the location address.Alarm output. Open-drain. Note that the ALARM output generates alarm signals only in external power mode.