Detailed Description

The MAX30207 temperature sensor provides 16-bit temperature measurements with 0.005°C resolution and ±0.1°C accuracy over a +30°C to +50°C temperature range and ±0.3°C accuracy over a 0°C to +70°C temperature range. The device communicates over a 1-Wire bus that requires only one data line and ground for communication with a microcontroller. In addition, the device derives power directly from the data line using parasite power, eliminating the need for an external power supply. Requiring so few pins enables the device to be placed in a tiny 2mm x 2mm LGA package. This form factor allows the device to be placed apart from the printed circuit board using just two wires to easily measure a remote object such as the human body, eliminating the challenges when mounting the device on the board. The device operates properly over a -40°C to +85°C temperature range without any damage.

Each device has a unique 64-bit serial code, allowing multiple MAX30207 devices to function on the same 1-Wire bus. Therefore, it is simple to use one microcontroller to control many devices distributed over a large area. The 64-bit ROM stores the device’s unique serial code. The memory mapped registers contain a data FIFO storing up to 32 measurement results from the temperature sensor. In addition, it also provides access to the 2-byte high alarm trigger and 2-byte low alarm trigger registers (AH and AL). The AH and AL registers are volatile and don’t retain data when the device is powered down.

The 1-Wire bus protocol implements bus communication using one control line. The control line requires a weak pullup resistor as all devices are linked to the bus through a three-state or open-drain port (i.e., the MAX30207’s DQ pin). In this bus system, the microcontroller (master device) identifies and addresses devices on the bus using each device’s unique 64-bit code. Because each device has a unique code, the number of devices that can be addressed on one bus is limited only by the bus capacitance. The 1-Wire bus protocol, including detailed explanations of the commands and time slots, is covered in the 1-Wire Bus System section. Additionally, the three GPIO pins can be configured as digital inputs, outputs, or special functions. When configured as digital inputs, they can be used as address bits to provide location information to the master device. This is achieved by connecting each of the three GPIO pins to the DQ or GND pins, allowing up to 8 unique locations per part number version (MAX30207, MAX30207A, MAX30207B, and MAX30207C). The device operates without an external power supply. Power is supplied through the 1-Wire pullup resistor to the DQ pin when the bus is high. The high bus signal also charges an external parasitic power capacitor (C_EXT), which then supplies power to the device when the bus is low. This method of deriving power from the 1-Wire bus is referred to as 'parasite power'.

The device’s core functionality is its direct-to-digital temperature sensor. The device powers up in a low-power standby state. There are two ways to initiate a temperature measurement. The 1-Wire bus master can issue a Convert T [0x44] command or configure GPIO1 as a rising edge activated start conversion input, which allows temperature conversions to be triggered by an external signal. The 1-Wire bus must remain idle while connecting a strong pullup on the DQ line for the duration of the conversion period.

Following the conversion, the resulting temperature sensor data is stored in the FIFO memory as a 2-byte temperature word and the device returns to the standby state. It is possible to sample up to 40Hz when accounting for startup time, integration time, and 1-Wire communications per sample. Sampling at high rates can lead to self heating that may be noticeable.

The output temperature data is calibrated in degrees Celsius. The temperature data is stored as a left-justified, 16-bit sign-extended two’s complement number as described in Table 7 where the MSB determines the sign of the temperature with an MSB of 1 indicating a negative temperature and an MSB of 0 indicating a positive temperature. Table 1 gives examples of digital output data and the corresponding temperature reading for 16-bit resolution conversions.

To calculate the temperature from the measurement result, convert the two's complement formatted data word to its signed decimal count value and use the following equation.

T = Decimal Value x 0.005

For example, if the result is 0x1CE8 then convert to decimal 7400, yielding a temperature of T = 7400 * 0.005 or 37°C.

After the device performs a temperature conversion, the temperature value is compared with the user-defined two’s complement alarm trigger values stored in the 2-byte Alarm High and 2-byte Alarm Low registers. Alarm High and Alarm Low Registers use the same format as the 2-byte FIFO temperature data word as shown in Table 7. The alarm high threshold, AH, is programmed in registers ALARM_HI_MSB (0x10) and ALARM_HI_LSB (0x11). The alarm low threshold, AL, is programmed in registers ALARM_LO_MSB (0x12) and ALARM_LO_LSB (0x13).

If the measured temperature is lower than AL or higher than AH, an alarm condition exists and corresponding status bit, TEMP_LO or TEMP_HI, is set in the STATUS register (0x00). When the alarm condition is detected and the corresponding interrupt enable bit, TEMP_LO_EN or TEMP_HI_EN, is set in the INTERRUPT ENABLE register (0x01), an alarm flag is set inside the device. If GPIO0_MODE (0x20) is set to 0x03, then a hardware interrupt asserts on the GPIO0 pin. The status bits, alarm flag, and hardware interrupt stay asserted until the STATUS register (0x00) is read through the serial interface. The alarm flag only clears when STATUS is read. If the alarm flag is set and the next result does not trip the flag, then the flag remains set. The default value for AH is 0x7FFF (163.835°C) and default value for AL is 0x8000 (-163.84°C).

The master device can execute an Alarm Search [0xEC] command to read the alarm flag status of all MAX30207 devices on the bus. All devices with a set alarm flag respond to the command, allowing the master to determine which devices have experienced an alarm condition. If the alarm settings change while the device is under an alarm condition, the alarm status must be cleared and another temperature conversion executed to update the alarm condition.

The MAX30207 provides access to three GPIO pins, which can be used to provide additional functionality as shown in Table 2. GPIO0 can be configured to output an active low interrupt. The interrupt on GPIO0 is triggered based on selectable status bits in the INTERRUPT_ENABLE[0x01] register. By setting one or more of the available bits in the INTERRUPT_ENABLE register, the flag for an interrupt is raised if the corresponding status register bit is set and GPIO0_MODE[1:0] in the GPIO_SETUP [0x20] register is set to 11. GPIO1 can be configured as an input for a temperature conversion. When GPIO1_MODE[1:0] in the GPIO_SETUP register is set to 11, a rising edge on GPIO1 initiates an external temperature conversion.

The 1-Wire bus system uses a single bus master to control one or more slave devices. The MAX30207 is always a slave. When there is only one slave on the bus, the system is referred to as a single-drop system; if there is more than one slave on the bus, the system is referred to as a multidrop system. All data and commands are transmitted least significant bit first over the 1-Wire bus.

The 1-Wire bus has, by definition, only a single data line. Each device (master or slave) interfaces to the data line through an open-drain or three-state port. This allows each device to release the data line when the device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the MAX30207 (the DQ pin) is open-drain with an internal circuit equivalent to that shown in Figure 1.

​The 1-Wire bus requires an external pullup resistor. Thus, the idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state until the transaction resumes. Infinite recovery time can occur between bits as long as the 1-Wire bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480μs, all components on the bus are reset. Additionally, to ensure the device has sufficient supply current during temperature conversions, it is necessary to provide a strong pullup (such as a MOSFET) on the 1-Wire bus whenever temperature conversions are performed.

The transaction sequence for accessing the device is as follows:

• Step 1: Initialization
• Step 2: ROM command (followed by any required data exchange).
• Step 3: MAX30207 Function command (followed by any required data exchange).

The bus master must follow this sequence every time a slave device is accessed. Slave devices do not respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search ROM [0xF0] and Alarm Search [0xEC] commands. After issuing either of these ROM commands, the master must return to Step 1 in the sequence.

The Skip ROM command addresses all devices on the bus simultaneously without sending out any ROM code information. This behavior speeds up the sending of function commands when there is only one slave on the bus and allows a master to send global commands when all slaves are the same device type.

For example, if all devices on the bus are MAX30207s, the master can make all devices perform simultaneous temperature conversions by issuing a Skip ROM command followed by a Convert T [0x44] command.

The Skip ROM command is also useful when there is only one MAX30207 device on the 1-Wire bus since, in this case, there is no need to distinguish between devices by sending the 64-bit ROM code.

After the bus master uses a ROM command to select a device, the master can issue one of the device function commands. These commands allow the master to write to and read from the device’s register memory, initiate temperature conversions, and reset the device. Table 3 summarizes the device function commands, and Figure 2 illustrates the overall one-wire command sequence to implement each function command.

The Convert T command initiates a single temperature conversion. Both CRC bytes must be read by the 1-Wire master before the conversion starts. Following the conversion, the resulting temperature sensor data is stored in the FIFO memory and the device returns to its standby state. Within 10μs (max) after the second CRC byte is read, the master must enable a strong pullup on the 1-Wire bus for the duration of the conversion (t_CONV), as described in the Parasite Power section.

A Convert T command sequence executes as follows:

1. Reset
2. Presence Pulse
3. ROM Command (Match or Skip ROM sequence)
4. Master TX: Convert T Command (0x44)
5. Master RX: Inverted CRC-16 (command)

The Write Register command writes data to the registers beginning at the specified address. It supports burst mode at the starting address and auto-increments after each byte.

A Write Register command sequence executes as follows:

1. Reset
2. Presence Pulse
3. ROM Command (Match or Skip ROM sequence)
4. Master TX: Write Register Command (0xCC)
5. Master TX: Starting Register Address
6. Master TX: Length Byte (number of bytes to write - 1); 0 to 255
7. Master TX: Write Register Data (n-bytes)
8. Master RX: Inverted CRC-16 (command + starting address+ length byte + write register data)

The Read Register command reads data from the registers beginning at the specified address. It supports burst mode at the starting address and auto-increments after each byte.

A Read Register command sequence executes as follows:

1. Reset
2. Presence Pulse
3. ROM Command (Match or Skip ROM sequence)
4. Master TX: Read Register Command (0x33)
5. Master TX: Starting Register Address
6. Master TX: Length Byte (number of bytes to read - 1); 0 to 255
7. Master RX: Read Register Data (n-bytes)
8. Master RX: Inverted CRC-16 (command + starting address+ length byte + read register data)

The Soft Reset command resets all configuration registers and the device returns to its standby state.

The Soft Reset command executes as follows:

1. Reset
2. Presence Pulse
3. ROM Command (Match or Skip ROM sequence)
4. Master TX: Soft Reset Command (0x82)
5. Master RX: Inverted CRC-16

The MAX30207 uses a strict 1-Wire communication protocol to ensure data integrity. Several signal types are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. Except for the presence pulse, the bus master initiates all falling edges. The MAX30207 can communicate at two different speeds: standard speed and overdrive speed. The MAX30207 defaults to standard speed on initial power on or reset. While in overdrive mode, the fast timing applies to all waveforms.

To transition from the idle to active state, the voltage on the 1-Wire line must fall from V_PUP to below the threshold V_TL. Conversely, the voltage must rise from V_ILMAX to above the threshold V_TH to transition from the active to idle state. The time required for the voltage to rise is represented by ε in Figure 3. The duration of ε depends on the pullup resistor (R_PUP) and the total capacitance of the 1-Wire bus. The voltage V_ILMAX only determines the MAX30207 logic level and does not affect event triggering.

Figure 3 illustrates the initialization sequence required to begin any communication with one or more MAX30207s. A reset pulse followed by a presence pulse indicates that the devices are ready to receive ROM commands. If the bus master uses slew-rate control on the falling edge, it must pull down the line for t_RSTL + t_F to compensate for the longer falling edge. A t_RSTL duration of 480μs or longer resets the bus and returns all devices to standard speed. If the MAX30207 is in overdrive mode and t_RSTL is shorter than 80μs, the device remains in overdrive mode. If the device is in overdrive mode and t_RSTL is between 80μs and 480μs, the device resets with an undetermined communication speed.

The bus master enters receive mode after it releases the bus at the end of t_RSTL. The 1-Wire bus is then pulled to V_PUP through the pullup resistor. When the threshold V_TH is crossed, the MAX30207 waits for t_PDH and then transmits a presence pulse by pulling the line low for t_PDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at t_MSP.

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Data communication with the MAX30207 takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. Figure 4 to Figure 6 show how the write and read time slots are defined.

All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V_TL, the MAX30207 starts its internal timing generator. This generator determines when the data line is sampled during a write time slot and how long data is considered valid during a read time slot.

​

For a write 0 time slot, the voltage on the data line must stay below the V_TH threshold until the write 0 low time t_W0L(MIN) expires. For a write 1 time slot, the voltage on the data line must have crossed the V_TH threshold before the write 1 low time t_W1L(MAX) expires. For the most reliable communication, the voltage on the data line must not exceed V_ILMAX during the entire t_W0L or t_W1L window. After crossing the V_TH threshold, the MAX30207 must wait for the recovery time t_REC before it is ready for the next time slot.

A read-data time slot begins like a write 1 time slot. The voltage on the data line must remain below V_TL until the read low time t_RL expires. During the t_RL window, when responding with a 0, the MAX30207 pulls the data line low. Its internal timing generator determines when this pulldown ends and the voltage rises again. When responding with a 1, the MAX30207 does not hold the data line low, and the voltage rises as soon as t_RL elapses.

The sum t_RL + δ (rise time) defines the start of the master sampling window and the internal timing generator of the MAX30207 defines the end ( t_MSR(MIN) to t_MSR(MAX)). The master sampling window is the period of time in which the master must perform a read of the data line. For the most reliable communication, t_RL should be as short as permissible, and the master should read close to but no later than t_MSR(MAX). After reading from the data line, the master must wait until t_SLOT expires. This guarantees sufficient recovery time, t_REC, for the MAX30207 to prepare for the next time slot. Note that t_REC applies only to a single MAX30207 attached to a 1-Wire line. For multidrop network configurations, t_REC must be extended to accommodate the additional 1-Wire device input capacitance.

The MAX30207's parasite power circuit allows it to operate without a local power supply. Parasite power is useful for space constrained applications or applications that require remote temperature sensing away from the main PCB. Figure 7 shows the device’s parasite-power control circuitry, which 'steals' power from the 1-Wire bus through the DQ pin when the bus is high. The parasite power capacitor, C_EXT, stores charge while the DQ line is high. This stored charge is used to power the device while the bus is low.

In the parasite-power mode, the 1-Wire bus and C_EXT provide the device with sufficient current to execute most operations as long as the specified timing and voltage requirements are met (see the Electrical Characteristics tables). However, the conversion current can reach 100μA (max) while the device performs a Convert T [0x44] command. During conversion, the current can exceed the C_EXT supply capability and may cause an unacceptable voltage drop across the weak 1-Wire pullup resistor. To ensure the device has sufficient supply current, provide a strong pullup on the 1-Wire bus when performing temperature conversions. This can be accomplished using an external MOSFET to pull the bus directly to the rail, as shown in Figure 7. Alternatively, the bus master can provide the supply path if it has an internal, weak pullup that can be switched directly to the rail. The 1-Wire bus must switch to the strong pullup within 10μs (max) after a Convert T [0x44] and CRC-16 read command sequence completes, and the bus must be held high by the strong pullup during the conversion (t_CONV). No other activity can take place on the 1-Wire bus until the temperature measurement is completed.

To minimize current, the MAX30207 enters standby when inactive. In the standby mode, all blocks are shutdown except for a low power input monitor circuit and the volatile register bits. The device only exits the standby mode when the 1-Wire master pulls down the bus.

When the part first turns on, the 1-Wire bus should remain high for at least 5 RC time constants, (High time > 5 x R_PULLUP x C_EXT), to fully charge C_EXT before sending the first 1-wire reset.

Each device contains a unique 64-bit code stored in ROM, the structure of which is shown in Figure 8. The 8 least significant bits of the ROM code contain the device’s 1-Wire family code, 0x54. The next 48 bits contain a unique serial number. The 8 most significant bits contain a Cyclic-Redundancy-Check (CRC) byte calculated from the 56 bits of the serial number and family code. A detailed explanation of the CRC bits is provided in the CRC Generation section. The 64-bit ROM code and associated ROM function control logic allow the device to operate as a 1-Wire device using the protocol detailed in the 1-Wire Bus System section. The 8-byte ROM code is transmitted LSB first.

The CRCs provide the bus master with a method of data validation when data is read from the device. To verify data is read correctly, the bus master must recalculate the CRC from the received data and then compare this value to the CRC. If the calculated CRC matches the read CRC, the data is received error free. The comparison of CRC values and the decision to continue with an operation are determined entirely by the bus master. There is no circuitry inside the device that prevents a command sequence from proceeding if the device CRC does not match the value generated by the bus master.

MAX30207 has two CRC Generators:

• 8-bit CRC for ROM Code.
• 16-bit CRC for all 1-Wire commands.

The 8-bit ROM Code CRC is calculated from the lower 56 bits read of the ROM code. This 8-bit CRC forms the upper 8 bits of the 64-bit ROM Code.

The equivalent polynomial function of the 8-bit CRC  is: CRC = X⁸ + X⁵ + X⁴ + 1.

The bus master can recalculate the CRC and compare it to the CRC values from the MAX30207 using the polynomial generator shown in [[8-Bit CRC State Machine]. This circuit consists of a shift register and XOR gates, and the shift register bits are initialized to 0. Starting with the least significant bit of byte 0 of the ROM code, one bit at a time should be shifted into the shift register. After shifting in the 56th bit of the ROM code, the polynomial generator contains the recalculated CRC. Next, the 8-bit ROM code CRC from the device must be shifted into the circuit. At this point, if the recalculated CRC is correct, the shift register contains all 0s. Additional information about the Maxim Integrated^® 1-Wire CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton® Products.

The Command CRC for the 1-Wire device function commands is calculated from the command sequence that includes the Command, Register Address, Length-1, and data bytes. The inverted 16-bit CRC is read by the 1-wire bus master at the end of each command sequence and is transmitted by the MAX30207 LSB first.

The equivalent polynomial function of the 16-bit CRC  is: CRC = X¹⁶ + X¹⁵ + X² + 1.

The bus master can recalculate the CRC and compare it to the CRC values from the MAX30207 using the polynomial generator shown in Figure 10. This circuit consists of a shift register and XOR gates, and the shift register bits are initialized to 0. Starting with the least significant bit of the command sequence, one bit at a time should be shifted into the shift register. After shifting in the last bit, the polynomial generator contains the recalculated CRC. Next, the 16-bit Command CRC from the device must be shifted into the circuit. At this point, if the recalculated CRC is correct, the shift register contains all 0s. Additional information about the Maxim Integrated^® 1-Wire CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton® Products.

In the Table 4 example, it is assumed there are multiple devices on the bus. The bus master initiates a temperature conversion in a specific MAX30207 and then reads its Temperature Data registers and recalculates the CRC to verify the data.

In the Table 5 example, there is only one device on the bus. The master writes to the alarm high and alarm low registers in the device’s Register Map and then reads the STATUS(0x00) register and recalculates the CRC to verify the data.

The FIFO is 32 samples long and is designed for 16-bit Temperature Data. The Master does a burst read of two bytes starting at register 0x08 to read one 16-bit  temperature sample, referred to as a word, from the FIFO. The Master reads 2N bytes from the FIFO to get N samples.

There are seven registers that control how the FIFO is configured and read out. These registers are illustrated below.

FIFO_DATA[7:0] is a read-only register to retrieve data from the FIFO. Each 2-byte temperature word is read from FIFO_DATA by burst reading 2N-bytes starting at register address 0x08. A 2N-byte burst read reads N temperature words from the FIFO and advances the FIFO_RD_PTR by N, i.e., if 6 bytes (3 temperature words) are read from the FIFO, the FIFO_RD _PTR increments by 3.

Table 7 shows the Temperature Data format in the FIFO.

Table 8 shows the order in which the two bytes of the Temperature Data are read through the serial interface.

When determining the number of words in the FIFO, it is a best practice to read both the FIFO_DATA_COUNT[5:0] and OVR_COUNTER[4:0] before a FIFO data read to insure the FIFO has not overflowed and data is overwritten. The following pseudo-code shows the typical program flow:

FIFO_WR_PTR[4:0] and FIFO_RD_PTR[4:0] are available for debug. They can also be used to calculate the number of available samples but note that there is an ambiguous case when the FIFO contains 0 or 32 words. In both cases, FIFO_WR_PTR and FIFO_RD_PTR both point to the same FIFO address. Look at the FIFO_DATA_COUNT[5:0] to know if there are 0 or 32 words in the FIFO.

The FIFO_A_FULL[4:0] field in the FIFO Configuration 1 (0x09) register sets the watermark for the FIFO and determines when the A_FULL bit in the STATUS (0x00) register is asserted. The A_FULL bit is set when the FIFO contains 32 minus FIFO_A_FULL[4:0] words. For example, when FIFO_A_FULL is set to 2, the flag is set when the 30^th word is written to the FIFO. When the FIFO almost full condition is met, the A_FULL bit is asserted in the STATUS register. If the A_FULL_EN bit in the INTERRUPT_ENABLE (0x01) register is set and GPIO0_MODE = 0x3 in the GPIO_SETUP (0x20) register, then the interrupt is asserted on the GPIO0 pin. This condition prompts the applications processor to read samples from the FIFO before it overflows.

The bus master can read both the FIFO_WR_PTR and FIFO_RD_PTR to calculate the number of words available in the FIFO, or read the OVF_COUNTER and FIFO_DATA_COUNT registers to determine how many words to read from the FIFO_DATA register.