Detailed Description

The registers will contain the reset values specified in the Register Map section of the data sheet upon power-up. It is necessary for certain bit fields in particular registers to be programmed with fixed values that are different from the power-on reset values. These register bit fields and the required values are given in Table 1. These values must be programmed whenever the IC is power-cycled. Note that these bits are described as “Reserved" in the data sheet. Nevertheless, for these reserved bits alone, the values indicated must be programmed.

Table 2 includes the default register bit values with the above specified bits programmed, as in Table 1.

The MAX2771 integrates two low-noise amplifiers, one for the L1 band (high band) and the other for the L2/L5 band (low band). Both inputs require AC-coupling capacitors. Bits LNAMODE in the Configuration 1 register control the modes of the two LNAs. See Table 2. The high-band LNA input impedance is matched to 50Ω at a frequency of 1575MHz, providing the specified high-band external matching circuit is used. The low-band LNA input impedance is matched to 50Ω at a frequency of 1227MHz, providing the specified low-band external matching circuit is used.

The output of each LNA is brought out to a separate pin. The output impedance of the high-band LNA is matched to 50Ω at frequency of 1575MHz, and the low-band LNA input impedance is matched to 50Ω at a frequency of 1227MHz.

The MAX2771 includes a quadrature mixer to output low-IF, or zero-IF, I and Q signals. There are two inputs to the mixer; one for high-band and the other for low-band. The high-band mixer input impedance is matched to 50Ω at a frequency of 1575MHz, while the low-band mixer input impedance is matched to 50Ω at a frequency of 1227MHz. The quadrature mixer requires a low-side LO injection. The output of the LNA and the input of the mixer are brought off-chip to facilitate the use of a SAW filter. On the MAX2771, the RF signal has been made accessible between the first LNA stage output and mixer input. If filtering is not desired, these pins can be connected through a coupling capacitor. However, filtering introduced at this point has minimal effect on the excellent sensitivity of the receiver. For example, for typical device parameters, a SAW filter with 1dB insertion loss would degrade cascaded NF (and therefore receiver sensitivity) by only about 0.15dB. While no external filtering is required for stand-alone applications, coexistence with cellular or Wi-Fi transmissions in close proximity may require additional filtering to prevent compressing the receiver front-end. The mixer is configured for the desired band by the MIXERMODE[1:0] bits. See Table 4.

The MAX2771 integrates a 20-bit, sigma-delta, fractional-N synthesizer allowing the device to tune to a required LO frequency with an accuracy of approximately ±30Hz (when f_XTAL ≤ 32MHz). The synthesizer includes a 10-bit reference divider with a divisor range programmable from 1 to 1023, a 15-bit integer portion main divider with a divisor range programmable from 36 to 32767, and also a 20-bit fractional portion main divider. The reference divider is programmable through the RDIV bits in the PLL Integer Division Ratio register, and can accommodate reference frequencies from 8MHz to 44MHz. The reference divider needs to be configured so the Phase Frequency Detector comparison frequency falls between 0.05MHz and 32MHz. In Integer-N mode, if the integer division ratio is divisible by 32, setting the PWRSAV bit of the PLL Configuration Register to 1 will reduce the power consumed by the PLL.

The PLL loop filter is the only external block of the synthesizer. A typical PLL filter is the classic C-R-C network at the charge-pump output. For example, see the Typical Application Circuit for the recommended loop filter component values for f_COMP = 1.023MHz and loop bandwidth = 56kHz, with charge pump current of 0.5mA and L1 band VCO. To calculate the loop filter component values for different LO frequencies, refer to the Design & Development section of the MAX2771 product page. The desired integer and fractional divider ratios can be calculated by dividing the LO frequency (f_LO) by f_COMP. f_COMP can be calculated by dividing the TCXO frequency, f_TCXO, by the PLL reference division ratio, R_DIV. For example, let the TCXO frequency be 20MHz, R_DIV be 1, and the nominal LO frequency be 1575.42MHz. The following method can be used when calculating divider ratios supporting various reference and comparison frequencies:

$f_{\mathrm{COMP}}=\frac{f_{\mathrm{TCXO}}}{\mathrm{RDIV}}=\frac{20\mathrm{MHz}}{1}=20\mathrm{MHz}$

$\mathrm{LO\_Frequency\_Divider}=\frac{f_{\mathrm{LO}}}{f_{\mathrm{COMP}}}=\frac{1575.42\mathrm{MHz}}{20\mathrm{MHz}}=78.771$

Integer Divider = 78(d) = 000 0000 0100 1110 (binary)

Fractional Divider = 0.771 x 2²⁰ = 808452 (decimal) = 1100 0101 0110 0000 0100

In the fractional mode, the synthesizer should not be operated with integer division ratios greater than 251.

There are two LO tuning bands provided. These are referred to as the L1 band and L2/L5 band respectively. The L1 band is designed for L1 and Commercial Mobile Satellite Services (CMSS) such as Inmarsat used for SBAS. The L2/L5 band is for L2 and L5 bands. The selection of a band is done by programming the LOBAND bit in the PLL Configuration register. For example, if the desired LO frequency is 1227.6MHz, since this falls into the L2/L5 band, set LOBAND = 1. Assuming the same comparison TCXO frequencies as the previous example, the PLL divider ratio would be set to 1227.6/20 = 61.38.

Integer Divider = 61(d) = 000 0000 0011 1101 (binary)

Fractional Divider = 0.38 x 2²⁰ = 398459 (decimal) = 0110 0001 0100 0111 1011

The LD output provides an indication of the PLL lock state. Note that the lock detector requires a reference clock in order to operate.

The IF filter of the receiver can be programmed to be a lowpass filter or a complex bandpass filter by setting the bit FCENX bit in the Configuration 1 register to either 0 for lowpass filter mode or 1 for bandpass filter mode. See Table 5.

Also, the IF filter can be configured either as a 3rd-order Butterworth filter for reduced group delay or a 5th-order Butterworth filter for steeper out-of-band rejection by setting the bit F3OR5 either 1 or 0, respectively in the Configuration 1 register. See Table 6.

The two-sided 3dB corner bandwidth can be selected to be 2.5MHz, 4.2MHz, 8.7MHz, 16.4MHz, 23.4MHz, or 36MHz by programming the FBW bits in the Configuration 1 register. See Table 7. When the FCENX bit in the Configuration 1 register is set to 1, the lowpass filter becomes a complex bandpass filter and the center frequency can be programmed with the FCEN bits in the Configuration 1 register. The IF center frequency is adjustable in 127 steps with the 7-bit FCEN value. See the Applications Information section of this document for information on how to configure the desired IF filter center frequency. If the filter is configured as a lowpass filter, the FCEN bits are ignored and the center frequency of the filter is at 0Hz.

The narrow-band filter settings are designed to pass the first null-to-first null main lobe of narrowband signals such as GPS L1 (2.046MHz) or Beidou B1 (4.092MHz). The 8.7MHz setting is for the GLONASS L1 band. The 16.4MHz setting is for signals having an intermediate bandwidth greater than the narrow band signals, but not as wide as the 20.46MHz wide signals. For example, Galileo E1 (14.3MHz) or Galileo E6 (10.23MHz). The 23.4MHz setting is for the wide-band signals typically having main lobe bandwidth of 20.46MHz; for example, GPS L1 P(Y), modernized GLONASS L3OC or BeiDou B2. Finally, the 36MHz setting is designed to allow simultaneous reception of two constellations, specifically GPS and GLONASS in either the L1 or L2 bands. Simultaneous reception of GPS L1 and GLONASS L1 provides a greater selection of visible satellites, which in turn allows faster time to fix and a more accurate navigation solution.

The MAX2771 provides a control loop that automatically programs the PGA gain to provide the ADC with an input power that optimally fills the converter and establishes a desired magnitude bit density at its output. The AGC algorithm operates by counting the number of magnitude bits over 512 ADC clock cycles and comparing the magnitude bit count to the reference value provided through a control word (GAINREF) in the Configuration 2 register. The desired magnitude bit density is expressed as a value of GAINREF in a decimal format divided by the counter length of 512. For example, to achieve the magnitude bit density of 33%, which is optimal for a 2-bit converter, program GAINREF to 170, since 170/512 = 33%. See Table 8.

The MAX2771 features an on-chip ADC to digitize the down-converted GNSS signal. The ADC supports the digital output in three different formats: unsigned binary, sign and magnitude, or two’s complement format by setting the FORMAT bits in Configuration 2 register. See Table 9. The sampled output is provided in a 2-bit format (1-bit magnitude and 1-bit sign) by default, and also can be configured as 1-bit or 2-bit in both I and Q channels, or 1-bit, 2-bit, or 3-bit in the I channel only. If only the I channel is used, the Q channel can be disabled with the IQEN bits in the Configuration 2 register. See Table 10. MSB bits are output on the I1 or Q1 pins and LSB bits are output on the I0 or Q0 pins, for I or Q channel, respectively. In the case of 3-bit output data format, the MSB is output on I1, the second bit is on I0, and the LSB is on Q1. The Q ADC must be enabled in 3-bit output data mode by setting the IQEN bit to 1. The number of bits of the ADC can be configured through the BITS field in the Configuration 2 register. See Table 11. Figure 1 illustrates the ADC quantization levels for 2-bit and 3-bit cases and also describes the sign/magnitude data mapping. The variable T = 1 designates the location of the magnitude threshold for the 2-bit case. Also see Table 12. The maximum ADC sampling rate is 44MHz.

A 12-bit fractional clock divider is located in the clock path prior to the ADC and can be used to generate an ADC clock that is a fraction of the reference input clock. In fractional divider mode, the instantaneous division ratio alternates between integer division ratios to achieve the required fraction. For example, if the fractional output clock is 4.5 times lower frequency than the input clock, an average division ratio of 4.5 is achieved through an equal series of alternating divide-by-4 and divide-by-5 periods. The fractional division ratio is given by:

f_OUT/f_IN = LCOUNT/(4096 - MCOUNT + LCOUNT)

where LCOUNT and MCOUNT are the 12-bit counter values in the Clock Configuration 2 register. The fractional division ratio cannot exceed 0.5. This divider can be enabled or bypassed by using the FCLKIN bit in the Clock Configuration 1 register. Also the sampling clock, ADCCLK, can be taken either before or after the Reference Clock Divider/Multiplier depending on the ADCCLK bit setting. See Table 13. Note that REFCLK in this table is possibly the output of the REFCLK fractional divider.

Moreover, it is possible to take the ADC clock from outside the IC. If the EXTADCCLK bit in the Clock Configuration 1 register is 1, the ADC clock will be taken from the ADC_CLKIN pin instead of using the internally generated clock. This allows simple synchronization of multiple MAX2771 ICs to a common ADC sampling clock.

In the case where multiple MAX2771 devices are used in a system, and the ADCs are being clocked at the same rate, which is some fraction of the reference clock frequency, the ADC outputs of the devices will not necessarily be aligned in time. A baseband that is processing the outputs of multiple devices may need to include additional logic to align the ADC samples from each device.

To allow simple synchronization of the ADCs of each device, the ability to clock the ADCs from an externally applied clock is provided. If the EXTADCCLK bit in the Clock Configuration 1 register is 1, the ADC clock will be taken from the ADC_CLKIN pin instead of using the internally generated clock. In a multiple MAX2771 scenario, all devices are assumed to be running off the same TCXO clock. One device would be designated as the clock source and configured to output its ADC clock on its CLKOUT pin. This clock signal can then be buffered and distributed through an external clock tree. The buffered clocks are then input on the ADC_CLKIN pins of all MAX2771 devices (including the clock source), and all devices are configured to use this external clock as their ADC clock. Alternatively, the source of the clock may not necessarily be a MAX2771 but could be some clock source elsewhere in the system.

GNSS data is output from the ADC as the four logic signals (bit0, bit1, bit2, and bit3) that represent sign/magnitude, unsigned binary, or two’s complement binary data in the I (bit0 and bit1) and Q (bit2 and bit3) channels. The resolution of the ADC can be set up to 3 bits per channel. For example, the 2-bit I and Q data in sign/magnitude format is mapped as follows: bit0 = ISIGN, bit1 = IMAG, bit2 = QSIGN, and bit3 = QMAG. The data can be serial­ized in 16-bit segments of bit0, followed by bit1, bit2, and bit3. The number of bits to be serialized is controlled by the bits STRMBITS in the Configuration 3 register. This selects between bit0; bit0 and bit1; bit0 and bit2; and bit0, bit1, bit2, and bit3 cases. If only bit0 is serialized, the data stream consists of bit0 data only. If a serialization of bit0 and bit1 (or bit2) is selected, the stream data pattern consists of 16 bits of bit0 data, followed by 16 bits of bit1 (or bit2) data. This, in turn, is followed by 16 bits of bit0 data, and so on. In this case, the serial clock must be at least twice as fast as the ADC clock. If a 4-bit serialization of bit0, bit1, bit2, and bit3 is chosen, the serial clock must be at least four times faster than the ADC clock.

The ADC data is loaded, in parallel, into four holding registers that correspond to four ADC outputs. Holding registers are 16 bits long and are clocked by the ADC clock. At the end of the 16-bit ADC cycle, the data is transferred into four shift registers and shifted serially to the output during the next 16-bit ADC cycle. Shift regis­ters are clocked by a serial clock that must be chosen fast enough so that all data is shifted out before the next set of data is loaded from the ADC. An all-zero pattern follows the data after all valid ADC data are streamed to the output. A DATASYNC signal is used to signal the beginning of each valid 16-bit data slice. In addition, there is a TIME_SYNC signal that is output every 128 to 16,384 cycles of the ADC clock.

Given that the serial clock has to run multiple times faster than the ADC clock, the use of the DSP interface is limited to narrowband signals that do not require a high ADC sampling clock frequency.

The crystal clock input on pin 3 is used to generate internal clocks and a reference clock that is output to the baseband. The block diagram illustrating the clock distribution is shown in Figure 3. There is a 12-bit fractional pre-divider that optionally allows division of the XTAL clock by some fractional amount. In the fractional divider mode, the instantaneous division ratio alternates between integer division ratios to achieve the required fraction. For example, if the fractional output clock is 4.5 times lower frequency than the input clock, an average division ratio of 4.5 is achieved through an equal series of alternating divide-by-4 and divide-by-5 periods. The fractional division ratio is given by:

f_OUT/f_IN = LCOUNT/(4096 - MCOUNT + LCOUNT)

where LCOUNT and MCOUNT are the 12-bit counter values in the Clock Configuration 1 register. The fractional division ratio cannot exceed 0.5. This divider can be enabled or bypassed by setting the PREFRACDIV_SEL bit in the Clock Configuration 2 register to either 0 or 1.

The reference clock can then be optionally divided by either two or four, or multiplied by two or four. This is determined by the REFCLK bits in the PLL Configuration Register. See Table 14. This table ignores the fractional ratio. The maximum frequency of the pre-divided reference clock is 22MHz if the x2 option is selected, and 11MHz if the x4 option is selected. The ADC sampling clock can then be generated by a second fractional divider. This is described in the section on the ADC. The CLKOUT signal to the baseband can be selected to either be the output of the integer divider/multiplier block or the ADC clock. This selection is done through the CLKOUT_SEL bit in the Clock Configuration 2 register.

The ADC clock can either be selected to be the internally generated clock, or taken from outside the IC. The EXTADCLK register bit selects whether the ADCs are clocked from the internally generated clock, or use the clock provided on the ADC_CLKIN pin. This feature allows multiple MAX2771 devices connected to a common baseband IC to have synchronized ADC outputs.

The maximum clock frequency for any of these clocks is 44MHz.

A serial interface is used to program the MAX2771 for configuring the different operating modes. The serial interface is controlled by three signals: SCLK (serial clock), CSN (chip select), and SDATA (serial data). The interface is based on the industry-standard Serial Peripheral Interface (SPI). The MAX2771 is a SPI slave and the device responsible for programming the MAX2771, such as a microprocessor or baseband controller, is the SPI master. The SPI master will be referred to henceforth as the “host”. The host is responsible for driving SCLK, CSN, and SDATA. The MAX2771 only drives SDATA at certain times during the transaction so as to avoid bus contention with the master.

The transfer of a set of data between host and MAX2771 is referred to as a “SPI transaction”. An SPI transaction consists of 48 SCLK pulses. The base value of SCLK is low. Data on SDATA is output on the falling edge of SCLK and is sampled on the rising edge of SCLK by both host and the MAX2771.

The SDATA line is normally tri-stated by both the host and the MAX2771. It can only be driven by the MAX2771 during the latter part of a Read SPI transaction provided that CSN = 0. SDATA is driven by the host during the entire SPI transaction in the case of Write transactions, and only during the first part of Read transactions.

The first 12 bits transferred from host to the MAX2771 during an SPI transaction contain the address of the register to be accessed. The first 8 bits are always zero, while the last four bits are the address of the register. The 13th bit transferred from master to MAX2771 is the R/W bit. If R/W = 1, the transaction is a read and the MAX2771 will drive SDATA in the latter part of the transaction. If R/W = 0, the transaction is a write, and the host will continue to drive SDATA for the remainder of the transaction. The 14th through 16th bits are turnaround bits that are denoted TA. The purpose of these bits is to allow time for the bus to change direction in the case of a read and so avoid any possible contention for the bus. In the case of a read transaction, the host releases SDATA during this interval, and the MAX2771 does not yet start driving SDATA. In the case of a write transaction, the host can continue to drive SDATA during this interval. The value of the bits is irrelevant (don’t care). The remaining bits of the transaction are the data bits. The number of data bits will always be a 32 since all the registers in the MAX2771 are 32-bits wide.

Figure 4 shows a register read transaction. In this example, a 32 bit register is read by the host. The host first asserts CSN, begins driving SDATA with the register address preceded by 8 zeros and starts toggling SCLK. The MAX2771 samples the bits on SDATA on the rising edge of SCLK. After the address is output, the host outputs a R/W bit having value of 1 indicating this a read transaction. The next three bits are the TA bits during which the host releases the SDATA line. In this figure, SDATA is shown as tri-stated during this bit interval to emphasize that nothing is actively driving it. The MAX2771 can be configured to resistively pull up SDATA, pull it down, or apply a bus-hold during periods when it is not driving the bus. The MAX2771 then starts driving SDATA and outputting the 32 bits of the addressed register starting from the most significant bit. After the last bit has been output, the MAX2771 tri-states SDATA, and the host subsequently brings CSN high completing the transaction.

Figure 5 shows a register write transaction. In this example, a 32-bit register is written by the host. The host first asserts CSN, begins driving SDATA with the register address preceded by 8 zeros and starts toggling SCLK. The MAX2771 samples the bits on SDATA on the rising edge of SCLK. After the address is output, the host outputs a R/W bit having value of 0 indicating this a write transaction. The next bits are the TA bits. Since this is a write, the host may choose to continue driving SDATA during this interval. The next 32 SCLKs, the host outputs the 32-bit data to be written to the addressed register starting from the most significant bit. After the last bit has been output, the host tri-states SDATA, and subsequently brings CSN high completing the transaction.

If the host does not assert CSN, the MAX2771 will ignore any activity on SCLK or SDATA. This allows multiple MAX2771 devices to be connected to the SPI and controlled by one host. Only the MAX2771 that has its CSN input asserted will react to the host.

Figure 6 illustrates the timing relationships between the three signals of the three-wire interface. See Table 15.

The MAX2771 is sold in wafer die form in addition to the TQFN packaged part. An approximately to-scale diagram of the die is shown in Figure 7. If one views the die through a microscope with the same orientation, it will resemble the figure. The bonding pads are depicted as squares or octagons. At the bottom left corner of the die is the die ID text. This can be used as an aid for orientation. The dimensions of the die are 2585 microns (horizontal) x 2685 microns (vertical). A micron is one micrometer (10^-6m).

The bonding pad names match the names in the Pin Description table. For the packaged version of the IC, the GND bonding pads are down-bonded to an exposed paddle. The GND pads should be connected to the ground plane of the substrate to which the die is attached.

In order to provide information on the locations of the bonding pads, a Cartesian coordinate system is established with the origin at the center of the SDATA bonding pad at the bottom left corner of the die. The coordinate system is depicted in the die diagram. A positive X coordinate is to the right of the origin, and a negative X coordinate is the left of the origin. A positive Y coordinate is above the origin, and a negative Y coordinate is below the origin. Table 16 provides the X and Y coordinates of each pad. The list of pads starts at the top left corner of the die and proceeds counter-clockwise around the die. The coordinates are for the center of each pad. The dimensions are microns. As an example, the coordinates of the CSN are (X, Y) = (656.1, -293.9). Hence the center of the CSN pad is 656.1 microns to the right of, and 293.9 microns below, the center of the SDATA pad.

The packaged MAX2771 devices undergo final test in the factory using a load board. The wafer dice undergo wafer-sort testing. This results in some differences in a few of the electrical characteristics. This is due to the differences in testing a packaged part with an RF matching circuit on the test load board which provides a low inductance ground plane, and doing testing directly on a wafer. For example, some of the parameters, such as LNA gain, depend on having an RF-matching circuit. This match is available during packaged part testing, but not when testing a wafer. Another factor is that the wafer sort grounds have higher inductance than the ground plane on the final test board for packaged parts. The electrical characteristics specific to the die part are included in the Electrical Characteristics table.