The FCEN bits in the Configuration 1 register are used to set the center frequency of the IF filter when it is configured as a bandpass filter. The following equations are used to calculate the required setting of FCEN to obtain the target center frequency. The center frequency should not be set higher than 9MHz for any filter bandwidth.
For FBW = 000 corresponding to a 2.5MHz filter bandwidth, the center frequency is calculated using the following equation:
For FBW = 010 corresponding to a 4.2MHz filter bandwidth, the center frequency is calculated using the following equation:
For FBW = 001 corresponding to a 8.7MHz filter bandwidth, the center frequency is calculated using the following equation:
Here are some examples: If FBW = 000, and FCEN[6:0] = 1011000, then the 2.5MHz wide filter will be centered at approximately [(128 – 88)/2](0.195) MHz = 3.9MHz.
If FBW = 001, and FCEN = 1101001, then the 8.7MHz wide filter will be centered at approximately
[(128 – 105)/2](0.66) MHz = 7.6MHz.
The calculations give approximate center frequencies. The center frequency needs to be tuned empirically.
Some signals used for precision GNSS or modernized GNSS have wide bandwidths. For example, the GPS L1 P(Y) signal has a main lobe (first null spacing) of 20.46MHz, and the Galileo E6 signal is 10.23MHz wide. For such wideband signals, the use of the wideband low pass filter is recommended so as to fit the entire main lobe of the signal within the passband of the filter and by doing so, avoid reducing the SNR.
First, the LO frequency has to be tuned to the center of the wanted signal so as to down-convert the signal to DC. For the case of the GPS L1 P(Y) signal, the required LO frequency is 1575.42MHz. As an example, assume the TXCO frequency is 16.368MHz. Assume the PLL reference division ratio (RDIV) = 16, giving a comparison frequency of 1.023MHz. This allows use of the integer-N PLL. Set the INT_PLL bit in the PLL Configuration register to 1. The PLL integer division ratio (NDIV) needs to be set to 1575.42/1.023 = 1540.
The IF filter is configured as a low pass 5th-order Butterworth 23.4MHz filter. Configure FBW = 011, F3OR5 = 0, and FCENX = 0. The FCEN bits can be left untouched since they are ignored for the lowpass filter case. Set the filter pole at the mixer output to 36MHz by setting MIXPOLE = 1. The ADC sampling rate should be set to a few MHz beyond the double-sided passband of the IF filter which is 23.4MHz in this case. This is to avoid degradation due to aliasing of noise. The offset frequency (from the 3dB corner frequency) at which the attenuation is 20dB is 18.5MHz. Hence, an ADC sampling rate of at least two times this, or 37MHz, is required. With a 16.368MHz TCXO clock, it is not possible, given the limitations on fractional division ratio and maximum frequency of the clock multiplier, to generate a 37MHz clock internally. The ADC clock is, therefore, provided from an external source on the ADC_CLKIN pin and the EXTADCLK register bit set to use the externally applied ADC clock.
As a second example, assume reception of the Galileo E5a signal is desired. This has a bandwidth of 20.46MHz and is centered at a frequency of 1176.45MHz. Since this frequency is in the L2/L5 band, the LOBAND bit in the PLL Configuration register must be set to 1. Assuming the same TXCO and reference division ratios as in the prior example, this means the integer division ratio must be 1150. Again, since the center frequency is an integer multiple of 1.023MHz, the PLL can be operated as an integer-N PLL. (The use of a 1.023MHz comparison frequency is convenient since most GNSS carrier frequencies will be integer multiples of 1.023MHz.) Since this is also a 20.46MHz wide signal, the IF filter settings and ADC clock configuration are the same as the prior example.
For a final example, consider reception of the Galileo E1 signal. This is 14.3MHz wide and centered at the frequency of 1575.42MHz. Assuming the same conditions as the prior examples, the synthesizer will be programmed identically to the first example. The IF filter will be programmed identically to the first example except for the bandwidth. The 16.4MHz wide filter setting should be used instead (FBW = 111). An ADC sampling rate of at least 26MHz is required. In this case, it is decided to simply multiply the TXCO clock by 2 giving an ADC clock frequency of 32.7MHz.