Once the IC is powered, an internal power-on reset (POR) signal sets all the registers to their default states. All twelve switches are in the on state upon a POR (all LEDs are off). The LEDs remain off until a command is received by the UART. To ensure reliable operation, the IN supply voltage (VIN) must be greater than VIN-POR. If VIN falls below VIN-POR and the VDD regulator output falls below VDD_UVLO, the registers reset to their default state. The IN voltage must be greater than VIN-POR and VDD must be above VDD_UVLO for proper operation. The bypass switches remain in their default on state until the UART is used to enable LED dimming.
Internal Switches
Each switch connected between DRAINn and DRAINn-1 has a typical on-resistance of 0.06Ω. This measurement includes the on-resistance of the internal switch and the resistance of the bond wires to the DRAINn and DRAINn-1 pads. Each bypass switch, when driven to an off state, allows the string current to flow through the corresponding parallel-connected LED, turning the LEDs on. Driving the bypass switch to an on state shunts the current through the bypass switch and turns the LEDs off. Each bypass switch can have one, two, or three LEDs in series across it.
Power-up Sequence
To avoid LED flash while turning ON the power in the system, proper power up sequence has to be followed. First, the matrix manager device MAX25608/MAX25608B/MAX25608C power must be applied. The device comes up with all the switches ON as soon as it is powered up. The bit SW_GO_EN in register SW_GO (0x01) is 0. The current source driving the LEDs should be enabled after that and so now the current will flow through the closed switches of the device and LEDs will not light up. After that, the required PWM duty cycle can be set up through the UART interface and then the SW_GO_EN is set to 1. This way, the LEDs light up with the required duty cycle.
When the device is running and if the LED current source is disconnected/broken for some reason, the LEDs can light up because of the bias currents flowing through the source/drain pins of the device. The total bias current seen can be close to 180μA on the bottom-most switch drain pin. To avoid the lighting up of the LEDs, 10kΩ resistors can be added across the switches, if needed. This case of undesired LED lighting up can also be managed by setting the SW_GO_EN bit to 0 when there is a fault from the current source.
Spread Spectrum
The MAX25608 has spread spectrum turned on the charge pump oscillator clock for better EMI performance. The MAX25608B/C have spread spectrum turned off on the charge pump oscillator. The proprietary charge pump design gives a good EMI performance even without the spread spectrum option. Spread spectrum is internally turned OFF when a UART transaction happens. When an external clock is used, spread spectrum is used only for the charge pump in the spread-spectrum enabled device (MAX25608). PWM and UART use the external clock when the external clock is applied instead of internal clock. When an external clock is used, the clock frequency must be greater than 16x the UART baud rate frequency.
The MAX25608 device that has spread spectrum on may show flicker at a duty cycle of <5%. For <5% duty cycle applications with full duplex UART communication, use the MAX25608C to avoid flicker.
Programming Options
Pin Resistor Decode Table
Multiple devices can be used in a multidrop UART bus with an external μC acting as the controller. The resistor on RADDR is used to program the UART device ID.
Table 1. Device ID Table
DECODED VALUE OF RADDR RESISTOR
DEVICE ID
0x0
0x0
0x1
0x1
...
...
0xF
0xF
Resistor Programming Table
A resistor connected between pins RADDR and GND is used to configure the device ID, and the resistor connected between pins RGRADE and GND is used for LED binning. The IC provides 16 levels of detection between 0 and 1.2V on RADDR/RGRADE pins. The pins source 400μA, allowing the use of an external resistor between RADDR/RGRADE and GND to set the voltage level. See Table 2 for recommended RGRADE/RADDR resistor values.
Table 2. RADDR/RGRADE Recommended Values
RGRADE/RADDR[3:0] DECODE VALUE
RGRADE/RADDR RESISTOR VALUE (Ω, 1%)
0000
95
0001
200
0010
309
0011
422
0100
536
0101
649
0110
768
0111
909
1000
1050
1001
1210
1010
1400
1011
1620
1100
1870
1101
2150
1110
2490
1111
2870
PWM Dimming
The IC provides 12-bit programmable dimming on each individual switch. An internal 12-bit counter (COUNT) is generated according to the clock settings. The switch turns off when COUNT is equal to the delay set by the corresponding PSFT register and stays off until the COUNT exceeds the sum of PSFT and PWM duty-control registers. In this way, the duty cycle and relative phase shift of the individual switches can be set independently (see Figure 1).
Figure 1. PWM Dimming
PWM Clock and Synchronous Operation with Multiple Devices
The PWM clock for the IC can be selected from the internal oscillator or from an external clock source driving the CLKIN pin. When an external clock is applied, the PWM generation and the UART communication uses this external clock. The CLKOUT pin can be configured to pass either the CLKIN or the internal oscillator as an output to other devices. In this manner, a single clock signal can be used to synchronize all devices. The PWM clock source and CLKIN/CLKOUT function are configured through PWM_CLK[1:0] in the CNFG_GEN (0x02) register. The default value is from the internal oscillator with the CLKIN and CLKOUT disabled. When the part is configured for external clock and if the external clock is missing, the part automatically switches to the internal clock.
PWM dimming frequency is programmable by setting the value of the DIV[1:0] bits in the CNFG_GEN (0x02) register, which sets the divide ratio for both the internal (16.38MHz) and external clock sources. Note that if a different external clock source is used, the PWM frequency will scale as a ratio of internal (16.38MHz) to external clock frequency for a fixed frequency divider value.
Synchronized operation with multiple devices is achieved through the following steps:
1. Set the SW_GO_EN bit to 0.
2. Select the controller device based on the resistor on RADDR pin and set the PWM_CLK[1:0] bits in the CNFG_GEN (0x02) register to use the internal oscillator and CLKOUT active.
3. Select the peripheral devices individually based on the resistor on RADDR pin and set the PWM_CLK[1:0] bits in the CNFG_GEN (0x02) register to keep the CLKIN and CLKOUT active. Connect the CLKOUT of the controller device to the CLKIN of the first peripheral device and the CLKOUT of the first peripheral device to the CLKIN of the 2nd peripheral device and so on.
4. Use the Global write command to set the SW_GO_EN bit to 1. All the PWM clocks of the devices will be synchronized now.
Dimming With and Without Fade
Each switch of the IC can be independently programmed to perform dimming without fade transition or dimming with fade transition. For dimming without fade transition, the dimming changes from the initial value to the target value in one dimming cycle. For dimming with fade transition, the dimming changes transitionally step by step, starting from the initial value to the target value in multiple dimming cycles, following a predetermined exponential curve.
To enable dimming with fade transition, set the FADE bit to 1 and the DUTY bits to the target value for the specific switches. Each transitional step value is calculated using 12 bits according to the following formula:
DUTYnext = DUTYnow x CF
where DUTY is the duty cycle, and CF the constant factor.
CF = 1.0625 and CF = 0.9375 for an up transition and down transition, respectively.
DUTYnext continues to be updated according to the formula until DUTYnext reaches the target value.
The transition period is defined by the TDIM_ register for the switch. The number of transitional steps depends on the distance between the initial value and the target value. The maximum number of transitional steps from 1(/8,191) to 8,191(/8,191) is 115 steps. See Figure 2 for the up-transition curve.
The number of transitional steps depends on the distance between the initial value and the target value. The maximum number of transitional steps from 8,191(/8,191) to 1(/8,191) is 111 steps. See Figure 3 for the down-transition curve.
Duty-cycle steps smaller than CF update in one step.
Each step runs TDIM_ PWM dimming cycles, and each dimming cycle consists of 8,192 clock cycles by default, therefore tSTEP = TDIM_ x 8,192. The 8,192 clock cycles timer can also be changed to 16,384, 32,768, or 65,536 clock cycles by programming bits [3:2] in register address 0x02.
Figure 2. Up-Transition Curve
Figure 3. Down-Transition Curve
RTEMP
The RTEMP pin is an auxiliary 8-bit ADC input that is suitable for use with an external NTC resistive divider for monitoring external temperature. In this way, a remote NTC resistor can be used to monitor the external LED temperature for current derating and system monitoring. The 8-bit code is updated with a period of 200 microseconds and can be read back using the UART RTEMP register (0x15).
Fault Pin Behaviour
The FLT pin will assert whenever one or more of these conditions is present:
One or more floating domain gate drivers have detected an open-LED fault; in this case, the switch(es) with Open LED faults remain closed until the power is reset
One or more floating domain gate drivers have detected a short-LED fault condition
Thermal warning/shutdown
RGRADE pin is open, shorted to ground, or out of range
UART errors happen
LED Fault Detection and Protection
The IC is able to detect a shorted LED and an open LED. To detect and report a LED fault, several conditions must be met. First, the LED switch must be operating, then the duty cycle must be greater than 0 since both LED-open and LED-short detection require the switch to be open. Open-fault detection is possible with a PWM duty cycle of 100% and short detection is not possible with 100% PWM duty cycle. In general, it takes up to one dimming cycle to make sure these conditions have been met after a fault condition is applied. This period depends on the PWM dimming frequency.
LED Open-Fault Detection and Protection
An open-LED fault is triggered when the voltage between the individual LED switch DRAIN node and switch SOURCE node exceeds VOTH and is reported in register OPEN_LED_STAT (0x13). The switch is closed when an open-LED is detected and remains closed. By default, the open fault results in the FLT pin being driven low; however, open faults can be masked by writing 0b1 to the MSK_OPEN_LED bit in the CNFG_MSK (0x0C) register. If an open-LED fault is detected multiple times, it is recommended that the OPEN__LED_OVRD (0x09) register be updated to force the corresponding LED switch to remain closed continuously to provide a bypass for the faulty LED.
LED Short Detection
A short-LED fault is triggered when the voltage between the switch DRAIN node and the switch SOURCE node is below VSTH for an open switch condition, and is reported in the SHRT_LED_STAT (0x12) register. The LED short comparator is sampled at the end of each LED pulse to avoid false detections during the beginning of the pulse. No action is taken with the switch in response to detecting a short-LED fault, thus continuing to operate as programmed. The short fault, by default, results in FLT being driven low; however, short faults can be masked by writing 0b1 to MSK_SHRT_LED in the CFG_MSK (0x0C) register.
The Low Duty Threshold register (0x16) is used to filter out LED fault signals during short duty cycles when the voltage across the switch might not settle to a final value, causing an invalid detection of the Short LED condition. When the DUTY register of a switch is less than LOW_DUTY_TH, the SHORT_LED signal is masked and SHORT_LED_STAT is not asserted for that switch.
Unused Switches and Pins
If some of the switches in the IC are unused, it is recommended to SHORT the switches on the PCB board. All of the faults associated with these unused switches should be masked using the appropriate bits in CNFG_MSK_LED.
If the RTEMP/RGRADE pin is unused, connect it to ground.
The CLKIN pin should be grounded, except for the applications when it is needed to synchronize to an external clock.
The IC features an on-chip temperature-protection circuit to prevent the device from overheating.
When the die temperature rises above the thermal-warning threshold (+140°C), the TH_WARN bit is set, causing the FLT pin to be asserted but no action taken with the switches. If asserted, the FLT pin remains asserted until the die temperature drops below the thermal-warning threshold, and the TH_WARN register bit is cleared by writing a 1. To clear the TH_WARN bit, the die temperature must be below the thermal-warning threshold. The UART communication works as usual when the part hits thermal warning threshold.
When the die temperature rises above the thermal-shutdown threshold (+160°C), the TH_SHDN bit in STAT_GEN register (0x10) is set, causing the FLT pin to be asserted and all switches to either be closed (LEDs turned off) or opened (LEDs turned on), depending on the value of the TH_SHDN_ACT bit in CNFG_MSK_GEN (0x0C) register. The UART communication is active but the switches remain either open or closed till the thermal shutdown hysteresis level is reached. When the device recovers from thermal shutdown, it resumes operation from where it was before the thermal shutdown. The FLT pin remains asserted until the die temperature drops below the thermal-warning threshold, and both the TH_WARN and TH_SHDN bits are cleared in the STAT_GEN (0x10) register by writing 1 to both bits. The TH_WARN and TH_SHDN status bits are cleared on write.
UART Serial Interface
Overview
The MAX25608/MAX25608C include a full-duplex UART serial interface and the MAX25608B includes a half-duplex (supports CAN physical layer) UART serial interface to enable fully programmable matrix manager functionality. The system ECU/MCU acts as the UART controller, driving read/write packets on the Rx line and receiving packets on the Tx line. The Rx and Tx lines can connect up to 16 devices on a common bus using a star topology. The device address of each IC is pin-programmable using an external resistor to ground on the RADDR pin. Devices can be addressed individually using their Device ID[3:0]. They can also be simultaneously addressed using the General Call ID or by using the programmable Cluster Call ID value.
The baud rate of incoming UART packets on Rx is automatically detected by the device, from a minimum of 10kbps up to a maximum of 950kbps. The device then returns frames on the Tx line at the same baud rate, according to the packet format described in the UART Frame Format section.
Device Connections
The UART interface ensures compatibility with standard microcontrollers from a variety of manufacturers. The MAX25608B also enables the use of CAN transceivers for applications where the matrix manager is remote from the microcontroller. The Rx line should be driven by the microcontroller controller. It can be connected to an individual device or to multiple devices in a star topology. The Tx line is an open-drain output. Multiple devices can share the same Tx connection as well. No external timing reference is required, the device automatically detects the bit rate on each Rx packet and adjusts the bit rate of the Tx response accordingly.
UART Packet Format
The MAX25608/MAX25608C features full-duplex UART communication capabilities—it is able to send and receive data at the same time. Read and write packets can be sent back to back with a minimum delay of at least one bit period between each packet as shown in Figure 4. This format should also be followed for global/cluster commands for the MAX25608B. The 1-bit length delay is not needed if using two stop bits.
Spacing of one stop bit (1-bit length) between packets is needed.
Figure 4. Back-to-Back Write/Read Packets for MAX25608/MAX25608C
For the MAX25608B version, if using individual write or read commands, the next message may be sent only after the response frames have concluded and after a delay of 1-bit length. This means that for an individual write command, the next message may be sent after the ACK frame has concluded and after a 1-bit length delay, while for a read command, the next message may be sent after the three response frames have been sent and a 1-bit delay length. This format is illustrated in Figure 5 and Figure 6.
Figure 5. Back-to-Back Read Packet Format for MAX25608B
Figure 6. Back-to-Back Write Packet Format for MAX25608B
UART Frame and Interframe Format
Read/write packets are composed from multiple UART frames. Each frame consists of one start bit, eight data bits, one parity bit (even), and two stop bits. The parity bit will be high if the number of ones in the data bits is odd, otherwise it will be low.
Figure 7. Frame Format
Figure 8. Interframe Format
Between frames, there should be no delay between the second STOP bit and the start of the next frame START bit. If there is a delay between second STOP bit and the start of the next frame START bit, the delay should not exceed 0.5x the bit length minus 350ns. For example, if the baud rate is 950kbs, the delay should not exceed 176ns, and for a baud rate of 500kbps the delay should not exceed 650ns. If these conditions are violated, a bit-sampling error may occur. This will result in a failure to ACK and an assertion of one or more of the following STAT_UART bits: RX_CRC_ERR, RX_PL_PERR, RX_PL_STOP_ERR.
Rx Rise and Fall Times
When the Rx line is driving many of the devices (16x maximum devices can be connected), the capacitive loading on the Rx line becomes high, causing the rise and fall times to become longer. As shown in Figure 9, the Rx bit length generated inside the part is different than the real Rx bit length. If the difference between TR and TF starts to become longer than 30ns, the device will extract a slower baud rate. If longer rise and fall times cannot be avoided, a lower baud rate may be selected, or a buffer may be used to reduce the rise and fall times.
Figure 9. Rx Rise Time and Fall Time
Synchronization and Acknowledge Frames
Each read/write packet must begin with a special Synchronization (SYNC) frame. This is a UART frame containing the data x79. The device synchronizes to the baud rate starting with the start bit of the SYNC frame. Once the falling edge of the start bit is detected, an internal frame counter is started. This counter counts the number of system clocks throughout the SYNC frame. Once the rising edge of D0 is detected, a second level counter starts and counts the number of system clocks until the next level shift. Once the system detects the falling edge of D0, the level counter is compared to one half of the frame counter. The level counter gets reset on the falling edge of D0, and the number of clocks from D1 to the rising edge of D3 are counted. Once the rising edge of D3 is detected, the system compares the level counter again to one half of the frame counter. This process is then repeated a third time for bits D3 through D6. The level counter and half of the frame counter are compared a third time. If all three comparisons are positive, the SYNC frame is accepted as valid, and the baud rate is determined as the frame counter divided by 8. When an external clock source is used, the clock frequency has to be 16x higher than the highest baud rate used for proper extraction of baud rate.
Figure 10. SYNC Frame
Each response packet always begins with a special Acknowledge (ACK) frame. This is a UART frame containing the data xC3.
Figure 11. ACK Frame
Device ID and Address Frame Format
Each device in the star configuration should be assigned a unique device ID number using the resistor connected to the RADDR pin. There are 16 possible device IDs that can be assigned in this way, from x00 to x0F (see Table 2).
In addition to addressing devices individually, the device also supports Global Call and Cluster Call write commands. A Global write command addresses all devices on the bus. A Cluster call addresses all devices with a matching cluster call ID in the CNFG_UART register. To perform a Cluster call, first an individual write transaction must occur to assign a Cluster ID (CID) to a particular device (see CNFG_UART (0x07)). After each device of interest is given a CID, a Cluster call may be performed by setting the Global/Cluster bit to 1, setting the R/W bit to 0, and writing the 6-bit CID. Data can then be written to all devices with a matching CID. To perform a Global call, set the Global/Cluster bit to 1, the R/W bit to 0, and the address bits to 0x00. This will address all devices on the bus. When performing a Global/Cluster call, the device will not respond with an ACK frame. Back-to-back Global/Cluster call write packets with a 1-bit length delay can be sent with the MAX25608B device. Read commands cannot use the Global/Cluster Call option and must be addressed to a specific device ID.
The address frame data bits are assigned as follows: the MSB is the Global/Cluster call bit, the next 6 bits are the device ID, and the LSB is the Read/Write bit.
Figure 12. Device ID and Address Frame
Write Transactions
Each write packet consists of five UART frames on the Rx pin. The first frame is the SYNC frame. The second frame consists of the Global/Cluster call flag, then the 6-bit device ID, and then the R/W bit. The R/W bit is low for a write command. The third frame is the register of the address being written to. The fourth frame is the lower byte of the data being written. The fifth and final frame includes the upper 5 bits of the data being written along with the 3-bit CRC code. Upon receiving a valid write packet, the device responds with an ACK frame on the Tx pin for an individual write.
Figure 13. Write Packet
Read Transactions
Each read command consists of four UART frames on the Rx pin. The first frame is the SYNC frame. The second frame consists of the Global/Cluster call bit set low, then the 6-bit device ID, and then the R/W bit set high. The third frame is the register address being written to, which is set by the RADDR value. The fourth and final frame includes the 3-bit CRC code, with the remaining 5 data bits set to 0. Upon receiving a valid read command, the device responds with three frames on the Tx pin. The first frame is the ACK frame. The second frame is the lower 8 data bits of the register being read. The third frame is the 3-bit CRC code, followed by the 5 MSBs of the register being read.
Figure 14. Read Packet
CRC Error Checking
Read/Write transactions are protected using a 3-bit cyclic redundancy check (CRC) on the packet. The CRC is provided by the controller on last 3 data bits of each UART_RX packet. For a write transaction, the CRC is calculated using: the 6 data bits of the second frame along with the Global/Cluster bit and the R/W bit, the data byte of the third frame, the data byte of the fourth frame, and the 5 data bits of the fifth frame for a write transaction. For a read transaction, the same process is followed, excluding the fifth frame of data as it is not included during a read transaction. Concerning the calculation of the CRC itself, the 3 bits to be appended are calculated using the LSB of each frame first in a descending order. Meaning that, starting with the second frame, the CRC is calculated starting with the LSB of the data bits of the frame, then moves on the the third, and then stops at the fourth (for a read transaction) or at the fifth (for a write transaction). For response frames on read packets, the device appends its own 3-bit CRC code to the 13-bit read data using the same polynomial.
The CRC calculation uses the polynomial x3 + x1 + 1 with a starting value of 000.
Figure 15. Final Frame
The final frame contains the upper 5 bits of data and the 3 CRC bits.
UART Watchdog Function
The device UART Watchdog feature sets the switches into a preconfigured state in the event of UART communication bus failures. If the CNFG_WATCHDOG bits are set to a nonzero value set, the device asserts a UART_WATCHDOG fault when the UART_RX pin has been inactive for more than the time set by the CNFG_WATCHDOG bits. For lower baud rate applications, the watchdog timer should be configured to be longer than the spacing between the packets. The watchdog timer begins counting when there is no communication on the Rx line, including the space needed between the packets for the MAX25608B. When the UART_WATCHDOG fault is set, the FLT output is asserted low, and the state of the channel switches is set to the value of the WD_LED_STATE register. The default value of WD_LED_STATE is x00, which opens all 12 switches in the event of a watchdog fault. The fault can be masked by setting the MSK_UART_ERR bit in the CNFG_MASK_GEN register. The fault status is cleared by writing a 1 to the UART_WATCHDOG bit. When the fault status is cleared, the switches resume operation according to the values of the PWM registers.
UART Communication Error Handling
In the event that there is an error in communication on UART_RX, it asserts the relevant fault status bit in STAT_UART (x11) and asserts the FLT output. The UART communications faults can be masked by setting the MSK_UART_ERR bit. Faults are cleared by writing 1 to the STAT_UART bits. The following communications errors result in fault assertion:
UART Watchdog Timeout: UART_RX stops transitioning for more than the time set by the CNFG_WATCHDOG bits in the CONFG_UART register.
RX_TIMEOUT_ERR: If there is no communication on the Rx line for more than a 16-bit length between frames, this bit will be asserted. If a watchdog timer is set by CNFG_UART, the part will enter into the default LED state set by CNFG_WATCHDOG. Write a 1 to clear this fault to continue normal communication.
RX_CRC_ERR: Invalid CRC code detected on a UART transaction.
RX_SYNC_PERR: Parity error in the SYNC frame
RX_PL_PERR: Parity error in the payload frame
RX_SYNC_STOP_ERR: Rx SYNC frame stop bit error.
RX_PL_STOP_ERR: Stop error bit detected in Rx data frames.
RX_PL_START_ERR: Start error bit detected in Rx data frames.
Delay between frames exceeds half of a bit length minus 350ns.
UART Timeout Conditions
Timeout is defined as a period of time where the device will not acknowledge any inputs from the Rx line. The following list shows what conditions will cause timeout to occur.
35ms Timeout:
RX_SYNC_PERR
RX_SYNC_STOP
Incorrect SYNC frame
No Timeout:
RX_TIMEOUT_ERR-- This error will cause the switches to go to the state set by the WD_LED_STATE bits in the CNFG_WATCHDOG register.
