| Package Code | U28E+1C |
| Outline Number | 21-100182 |
| Land Pattern Number | 90-100069 |
| Thermal Resistance, Four-Layer Board: | |
| Junction-to-Ambient (θJA) | 33.6°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 3.3°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Positive Power-Supply Input. Bypass IN to PGND with at least a 1µF ceramic capacitor.Positive Input for the Input Current LimitNegative Input for the Input Current Limit. Add an RC low-pass filter from INN to INP to provide a filtered DC voltage from INP to INN. The resistor should be 100Ω and the capacitor 0.1µF.High-Side Power Supply for High-Side Gate Drive for Buck Section. Connect a 0.1μF ceramic capacitor from BST1 to LX1.Top Gate Drive for Buck Section of the MAX25603. Drives the gate of the high-side nMOS.Buck-Side Switching Node. LX1 pin swings from a diode voltage drop below ground up to VIN.Bottom Gate Drive for Buck Section of the MAX25603. Drives the gate of the low-side nMOS. A resistor from this pin to SGND also sets the switching frequency. Connect appropriate resistor from DL1 to SGND to set the switching frequency.Power Ground ConnectionBottom Gate Drive for the Boost Section of the MAX25603. Drives the gate of the low-side nMOS. A resistor from this pin to SGND also sets the switching frequency. Connect appropriate resistor from DL2 to SGND to set the switching frequency.Switching Node of Boost Section of the MAX25603. LX2 pin swings from a diode voltage drop below ground up to VOUT.Top Gate Drive for Boost Section of the MAX25603. Drives the gate of the high-side nMOS.High-Side Power Supply for High-Side Gate Drive for Boost Section. Connect a 0.1μF ceramic capacitor from BST2 to LX2.Positive Input to the Current-Sense Comparator for the Average-Current-Mode Controller.Negative Input to the Current-Sense Comparator for the Average-Current-Mode Controller.Positive LED Current-Sense Input. The voltage between ISP and ISN is proportionally regulated to 1.1V/5 or (VICTRL - 0.2)/5, whichever is less.Negative LED Current-Sense InputChannel 2 High Side Gate Drive. The GTP2 pin drives an external high-side pMOS PWM switch with a voltage swing from VOUT to (VOUT – 5V). Leave this pin unconnected if not used.Channel 1 High-Side Gate Drive. The GTP1 pin drives an external high-side pMOS PWM switch with a voltage swing from VOUT to (VOUT –5V). Leave this pin unconnected if not used.Overvoltage-Protection Input for the LED String. Connect a resistive divider between the output, FB, and GND. When the voltage on FB exceeds 1.24V, a fast-acting comparator immediately stops PWM switching. VOVP = 1.24 x (RFB1 + RFB2)/ RFB2.Active-Low, Open-Drain Fault Indicator Output. See the Fault Indicator (FLT) section.Compensation-Network Connection when SHUNT is low. For proper compensation, connect a suitable RC network from COMP1 to SGND.Compensation-Network Connection when SHUNT is high. For proper compensation, connect a suitable RC network from COMP2 to SGND.Signal Ground Connection5V Regulator Output. Connect a minimum 2.2μF ceramic capacitor from VCC to SGND for stable operation.Analog Dimming-Control Input. Connect an analog voltage from 0 to 1.3V for analog dimming of LED current. ILED = (VICTRL − 0.2V)/(5 × RLED). Bypass ICTRL to GND with at least a 10nF ceramic capacitor for noise filtering. If VICTRL > 1.3V, the capacitor is not needed and LED current is clamped to ILED = 1.1V/(5 × RLED).Drive this pin high when using PWM dimming across some LEDs in the string. SHUNT high enables compensation network on COMP2 and SHUNT low enables compensation network on COMP1.Drive EN1 to enable pMOS gate drive on GTP1 and turn on LED string connected to pMOS drain on GTP1. Drive EN1 low to disable gate drive on GTP1 and turn off LED string on GTP1. Drive with a PWM signal to implement PWM dimming on GTP1.Drive EN2 to enable pMOS gate drive on GTP2 and turn on LED string connected to pMOS drain on GTP2. Drive EN2 low to disable gate drive on GTP2 and turn off LED string on GTP2. Drive with a PWM signal to implement PWM dimming on GTP2.Exposed Pad. Connect EP to a large-area contiguous copper ground plane for effective power dissipation. Do not use as the main IC ground connection. EP must be connected to SGND.