| Package Code | T2444Y+4C |
| Outline Number | 21-100290 |
| Land Pattern Number | 90-0022 |
| THERMAL RESISTANCE, FOUR-LAYER BOARD | |
| Junction-to-Ambient (θJA) | 42.4°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 3.2°C/W |
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
data-opMAX25431ATGB%2FVY%2B
data-opMAX25431ATGB%2FVY%2BT
data-opMAX25431ATGA%2FVY%2BT
data-opMAX25431ATGA%2FVY%2B
Buck Low Side Gate DrivePower GroundNegative Input of the Input Side Current-Sense Amplifier. Connect CSN1 to the negative side of the input current-sense resistor.Positive Input of the Input Side Current-Sense Amplifier. Connect CSP1 to the positive side of the input current-sense resistor.Voltage Supply Input. IN powers up the internal linear regulator. Bypass IN to PGND with a ceramic capacitor as suggested in the Typical Application Circuit.High-Voltage Enable Input. Driving EN high enables the buck-boost controller.Slope Compensation for Peak Current Mode Control. Connect a resistor between SLP and AGND to set the desired slope compensation for the current feedback loop.Feedback Analog Input. Connect an external resistive divider from OUT to FB and AGND to set the desired output voltage. Connect to VCC to set the output voltage to 5V.Switching Frequency Setting. Connect a resistor between FSW and AGND to set the desired frequency.Error Amplifier Output. Connect the external compensation network of the feedback loop between COMP and AGND for stable operation.Open-Drain, Power Good Output Indicator. An external pullup is required.Connect FSYNC to an external frequency source for synchronization. SYNCOUT is available to output 180° out of phase clock for dual port synchronization.Switching Regulator Voltage Output. Connect recommended capacitor values between OUT and PGND as per the Typical Application Circuit.Negative Input of the Output Side Current-Sense Amplifier. Connect CSN2 to the negative side of the output current-sense resistor.Positive Input of the Output Side Current-Sense Amplifier. Connect CSP2 to the positive side of the output current-sense resistor.Analog Ground of the IC. Connect to ground plane reference of the PCB.Linear Regulator Output. VCC powers up the internal circuitry. Bypass with 4.7μF ceramic capacitor to AGND.Boost Low-Side Gate DriveBootstrap Capacitor for High-Side Driver of the LX2 Node. Connect a 0.1μF capacitor from BST2 to LX2.Boost High-Side Gate Drive.OUT to PGND Switching Output Node. High impedance when the part is off. Connect to one of the external inductor terminals.IN to PGND Switching Input Node. High impedance when the part is off. Connect to the other external inductor terminal.Buck High-Side Gate Drive.Bootstrap Capacitor for High-Side Driver of LX1 Node. Connect a 0.1μF capacitor between BST1 and LX1.Exposed Pad. EP must be connected to the ground plane on the PCB, but it is not a current-carrying path and is needed only for thermal transfer.