Applications Information

Applications Information Inductor Selection

Design of inductor is a compromise between the size, efficiency, control bandwidth, and stability of the converter. For a buck-boost application, selecting the right value of inductor becomes even more critical due to the presence of right-half-plane (RHP) zero in boost and buck-boost mode. A bigger inductance value would reduce RMS current loss in MOSFETs and core/winding losses in the inductor. On the other hand, it slows the control loop and reduces the frequency of the RHP zero that can cause stability concerns.

Start the inductor selection based on the inductor current ripple as a percentage of the maximum inductor current in buck mode using the equations below. Choose the highest inductance between LBUCK and LBOOST. Minimum duty cycle in buck or boost will yield the highest inductor current ripple.

L_{BUCK} > \frac{(V_{IN_MAX} - V_{OUT_MIN}) \cdot D_{BUCK_MIN}}{f_{SW} \cdot {ΔI}_{L}}

(eq. 1)

$L_{BOOST} > \frac{V_{IN_MIN} \cdot D_{BOOST_MAX}}{f_{SW} \cdot {ΔI}_{L} \cdot V_{IN_MIN}}$ (eq. 2)

${ΔI}_{L} = I_{OUT_MAX} \cdot LIR$ (eq. 3)

$D_{BUCK_MIN} = \frac{V_{OUT_MIN}}{V_{IN_MAX} \cdot η_{BUCK}}$ (eq. 4)

$D_{BOOST_MAX} = 1 - \frac{V_{IN_MIN} \cdot η_{BOOST}}{V_{OUT_MAX}}$ (eq. 5)

L_BUCK,L_BOOST:minimum inductance needed in buck mode and boost mode, respectively, in H.

f_SW: switching frequency in Hz.

V_{IN_MIN} ,V_{IN_MAX} : minimum and maximum voltage seen at the power stage input, respectively.

I_{OUT_MAX} : maximum DC output current supported in the application.

LIR:desired peak-to-peak inductor current ripple ratio. Ratio of ∆_IL/I_{OUT_MAX}.

D_{BUCK_MIN}, D_{BOOST_MAX} : minimum and maximum duty cycle in Buck and Boost mode, respectively.

η_BUCK, η_BOOST: efficiency at maximum load in buck mode and boost mode, respectively.

V_{OUT_MIN} : lowest output voltage seen in the application. For fixed PDO applications, use 5.15V (Vsafe5V).

V_{OUT_MAX} : highest output voltage seen in the application. 5.15V, 9V, 15V or 20V for fixed PDOs applications.

Select the final value of inductance considering the ripple in both regions of operation, inductor derating and RHP zero. Once the final value of inductance is selected, calculate the peak inductor current and choose an inductor with saturation current approximately 20% more than the peak inductor current. Low DCR helps achieve higher efficiency by reducing inductor conduction loss during high output power with low input voltage.

Example

P_{OUT_MAX} = 100W ; V_{IN_MIN} = 6V ; V_{IN_MAX} = 18V ; V_{OUT_MIN} = 5.15V ; V_{OUT_MAX} = 20V ; f_SW = 400kHz ; I_{OUT_MAX}=5A ; η_BUCK= η_BOOST = 95% ; LIR is chosen to be 55% to keep the inductor small.

For this example, L_BUCK > 3.5 uH and L_BOOST > 3.9 uH. Therefore, an inductor with a value of 4.7µH will be selected.

Inductor saturation current must be considered when choosing the inductor.

The high input current seen during low V_IN/High P_OUT conditions has an impact on the current saturation rating of the inductor and therefore its size. The MAX25431 advantage is its flexibility with regards to output power thanks to its scalable peak input current limit. When selecting the input current sense resistor value (R_CS1), consider the output power, inductor saturation current, minimum input voltage seen at the power stage but also the minimum V_BUS voltage to meet at the user port. When the peak input current reaches the I_OC1 threshold defined by R_CS1, the controller will automatically enter cycle-by-cycle input current limit which may cause V_BUS to droop below the minimum specification at the port. Cable compensation will not increase V_BUS in this condition as the input current (and therefore the input power) is limited.

Once the input sense resistor value is selected, the inductor saturation current rating (I_SAT) value can be chosen. The I_SAT value must be higher than the input peak I_LIM threshold by some safe margin to avoid saturating the core.

$I_{SAT} > I_{OC 1_MAX}$

$I_{SAT} > \frac{V_{OC 1_MAX}}{R_{CS 1}}$

Example

R_CS1 = 3mΩ and V_{OC1_MAX} = 60mV yields I_{OC1_MAX} = 20A, therefore:

$I_{SAT} > 20 A$

Input Capacitor Design

The input capacitor reduces peak currents drawn from the power source and minimizes noise and voltage ripple on the input caused by the circuit switching. In buck mode, input current is discontinuous with maximum ripple. The RMS current is shown in the following equation:

I_{RMS} = \frac{I_{OUT_MAX} \cdot \sqrt{V_{OUT} \cdot (V_{IN} - V_{OUT})}}{V_{IN}}

(eq. 6)

The maximum input RMS current occurs at V_IN = 2 x V_OUT. Substituting V_IN previously, the equation then becomes:

$I_{RMS_MAX} = \frac{I_{OUT_MAX}}{2}$ (eq. 7)

The input voltage ripple in buck mode is given by:

(eq. 8)

It is recommended to keep the input voltage ripple below 1% of the input voltage to limit noise that could be conducted through the battery harness.

Maximum input voltage ripple occurs in buck mode at a duty cycle of 0.5 and at max output current. Select a higher value for the final capacitor or bank of capacitors to account for DC Bias and tolerance derating.

Use the following equation to determine the input capacitance needed to meet the input voltage ripple requirement:

Example

f_SW = 400kHz ; I_{OUT_MAX}=5A ; D_BUCK= 0.5 ; C_{IN_TOL} = 10% ; C_{IN_DCBIAS} = 10% ; ∆V_{IN_MAX} = 12V * 0.01 = 0.12V

For this example, C_IN > 27μF.

Select the input capacitor that can handle the given RMS current at the operating frequency. Ceramic capacitors come with extremely low ESR and help reduce the peak-to-peak ripple voltage at the input voltage. Good quality electrolytic capacitors are also available with low ESR, which give higher capacitance at low cost.

Electrolytic (bulk) input capacitors help reduce input voltage drop during large load transients. ESR in bulk capacitors help dampen line transients. A good combination of electrolytic and ceramic capacitors can help achieve the target specifications and minimize cost.

Place a high-frequency decoupling ceramic capacitor to filter high di/dt and reduce EMI caused by Qt1 turn on. Choose a small package, such as 0402, with low ESL.

Choose a voltage rating of 50V for applications where a 40V load dump can be seen at the input.

Output Capacitor Design

Output capacitance is selected to satisfy the output load-transient requirements. During a load step, the output current changes almost instantaneously whereas the inductor is slow to react. During this transition time, the load-charge requirements are supplied by the output capacitor, which causes an undershoot/overshoot in the output voltage. Select a capacitor based on the maximum allowable overshoot/undershoot on the output voltage. Typically, the worst-case response from a load transient is in boost mode. Use the following equations to contain the undershoot within the given specifications in boost mode:

C_{OUT} \geq \frac{L \times ∆ {I_{LSTEP}}^{2}}{2 \times V_{SUP_MIN} \times D_{MAX} \times V_{UNDER}} + \frac{(∆ I_{LSTEP} \times ∆ t_{DELAY})}{V_{UNDER}}

where t_DELAY = Time delay for the next control pulse after a load step. For fixed-PWM mode, t_DELAY is the turn-off time in buck/boost mode.

Select the output capacitance to handle load transients in deep boost mode. t_DELAY is the delay for the PWM modulator to react after a load step. In PWM mode, the worst-case delay would be (1-D) x t_SW when the load step occurs right after a turn-on cycle. With the previous example values:

C_{OUT} \geq 120 μF

Once the output capacitance is selected, the output voltage undershoot/overshoot can be calculated for buck region of operation using the following equations:

V_{UNDER_BUCK} = \frac{L \times ∆ {I_{LSTEP}}^{2}}{2 \times (V_{SUP} - V_{O}) \times D_{MAX} \times C_{OUT}}

V_{OVER_BUCK} = \frac{L \times ∆ {I_{LSTEP}}^{2}}{2 \times V_{O} \times C_{OUT}}

Output-Voltage Setting

Connect FB to V_CC to enable the fixed output voltage (5V) set by a preset internal resistive voltage-divider connected between the feedback (FB) pin and AGND. To externally adjust the output voltage between 4V and 25V, connect a resistive divider from the output (OUT) to FB to AGND (Figure 1). Calculate RFB1 and RFB2 with the following equation:

R_{FB 1} = R_{FB 2} [(\frac{V_{O}}{V_{FB}}) - 1]

where V_FB = 1.25V (typ). See the Electrical Characteristics table.

Current-Sense Resistor Selection

The MAX25431 uses two external current-sense resistors for inductor current control and current-limit implementation. Input current-sense resistor feedback is used for the current loop, setting the peak current limit and PFM current limit. Output current-sense information is used for runaway current limit.

Select an input current-sense resistor based on the maximum input current for the application (typically at minimum at input voltage). The differential voltage across R_CS1 for input current-limit threshold is 50mV. Calculate the peak input current using this equation:

I_{INPEAK} = \frac{V_{O} \times I_{O}}{V_{SUPMIN}} + \frac{V_{SUPMIN} \times (1 - \frac{V_{SUPMIN}}{V_{O}})}{L \times f_{SW} \times 2}

Figure 1. Setting the Output Voltage for the MAX25431

Calculate the current-sense resistor by setting the peak current limit (I_LIM) slightly higher than the peak input current (I_INPEAK) calculated above.

R_{CS 1} = \frac{50 mV}{I_{LIM}}

Since one event of runaway current limit would make the controller enter hiccup mode, design the runaway current limit higher than the peak current to keep a safe margin. The MAX25431 has internal runaway current limit set to 50% higher than peak current limit (i.e., 75mV), which enables the designer to use the same current-sense resistors on input and output.

R_{CS 2} = \frac{75 mV}{I_{LIM - RUNAWAY}}

Slope Compensation

An external slope compensation is typically required for current-mode control due to its inherent instability. A properly designed current-mode control with external slope compensation removes the instability and provides noise immunity from current-sense signals. The MAX25431 offers a simple way to set the slope compensation by connecting a resistor between SLP pin and AGND. The resistor for slope compensation can be calculated using equation the below:

R_{SLOPE} = \frac{1.25 V \times 0.09}{V_{p 2 p}} \times \frac{1}{8 pF \times f_{SW}}

Design the slope compensation to lower the quality factor of the double pole at half the switching frequency of current-mode control (Q_P) given by equation:

Q_{P} = \frac{1}{π \times (m_{c} \times D' - 0.5)}

where m_C, the compensation ramp factor, is given by:

m_{c} = 1 + \frac{S_{e}}{S_{n}}

S_e = Slope of the external ramp

S_n = Rising slope of inductor current

V_p2p = The peak-to-peak voltage of the external slope compensation

Error-Amplifier Compensation Design

The MAX25431 uses an internal transconductance amplifier with its inverting input and output terminals available to the user for external frequency compensation, as shown in Figure 2.

The controller uses a peak current-mode-controlled architecture to regulate the output voltage by forcing the required current through the external inductor. The external current-sense resistor senses the inductor current information. The current-mode control splits the double pole in the feedback loop caused by the inductor and output capacitor into two single poles. One of the poles is moved to a high frequency outside the typical bandwidth of the converter, making it a single-pole system. This makes compensation easy with only Type II required to compensate the loop. In boost mode, an extra right-half plane (RHP) zero is introduced by the power stage to add extra phase delay in the control loop. To avoid any significant effect of the RHP zero on the converter stability, the compensation is designed such that the bandwidth is approximately 1/4 of the worst-case RHP zero frequency.

The design of external compensation requires some iterations to reach an optimized design. Care must be taken while designing the compensation for working in ‘deep’ boost mode and heavy load (V_{SUP_MIN}) as RHP zero frequency reduces.

A convenient way to design compensation for both buck and boost modes is to design the compensation at minimum input voltage and heavy load (deep boost mode). At this operating point, RHP zero is at its lowest frequency. Design the compensation to achieve a bandwidth close to 1/4 of the RHP zero frequency in deep boost mode. Verify the gain and phase margin with the designed compensation in buck mode. The closed-loop gain of the converter is a combination of the power-stage gain of the converter and error-amplifier gain.

Figure 2. Setting the Output Voltage for the MAX25431.

\frac{\overset{⏞}{V_{O}}}{\overset{⏞}{V_{C}}} = \frac{R_{L} \times (1 - D)}{G_{CS} \times 2} \times \frac{(1 + \frac{S}{ω_{ESR}}) \times (1 - \frac{S}{ω_{RHP}})}{(1 + \frac{S}{ω_{p_BOOST}}) \times F_{H} (s)}

where:

G_CS = Current-sense gain = R_CS1 x 24

R_CS1 = Sense resistor connected to CSP1:

ω_{P_BOOST} = \frac{2}{R_{L} \times C_{OUT}};

$ω_{ESR} = \frac{1}{R_{C} \times C_{OUT}};$

ω_{RHP} = \frac{R_{L} \times {(1 - D)}^{2}}{L};

F_{H} (S) = 1 + \frac{S}{ω_{N} \times Q_{P}} + {(\frac{S}{ω_{N}})}^{2}

Q_{P} = \frac{1}{π \times (m_{C} \times D' - 0.5)}; ω_{N} = \frac{π}{T_{SW}}

Error-amplifier transfer function:

H_{EA} (S) = g_{m} \times R_{DC} \frac{(1 + \frac{S}{ω_{Z_COMP}})}{(1 + \frac{S}{ω_{p 1_COMP}}) \times (1 + \frac{S}{ω_{P 2_COMP}})}

where:

ω_{Z_COMP} = \frac{1}{R_{ZERO} \times C_{ZERO}}

ω_{P 1_COMP} = \frac{1}{R_{DC} \times C_{ZERO}}

ω_{P 2_COMP} = \frac{1}{R_{ZERO} \times \frac{(C_{POLE} \times C_{ZERO})}{(C_{POLE} + C_{ZERO})}}

≅ \frac{1}{R_{ZERO} \times C_{POLE}} if

C_{POLE} < < C_{ZERO}

Closed loop gain:

Closed loop gain = Power stage gain x EA gain

External MOSFET Selection

Four external MOSFETs are required for the H-bridge buck-boost architecture supported by the MAX25431, as shown in the Typical Application Circuit. During the buck-mode of operation, Q_t2 remains on and Q_b2 remains off. Q_t1 and Q_b1 switch to regulate the output voltage. During the boost mode, Q_t1 remains on, Q_b1 remains off, and Q_t2 and Q_b2 switch to regulate the output voltage. In the buck-boost region, all four switches are used to control the output voltage. The MOSFETs must be selected based on certain critical parameters such as on-resistance, breakdown voltage, output capacitance, and input capacitances. A low R_DSON reduces the conduction losses in the MOSFET and a small gate/output capacitance reduces switching losses. Typically, a lower R_DSON MOSFET would have higher gate charge for the same breakdown voltage. Hence, a compromise must be made depending on conditions to which the MOSFET is subjected.

The MAX25431 comes with a 5V gate drive with a high current capability to support switching of 4 MOSFETs at high frequency. In the buck-boost region, the device switches between pure buck and boost modes to reduce the gate-drive current and increases the efficiency.

Boost Cap and Diode Selection

A boost-strap circuit is used to drive the floating gates of high-side switches Q_t1 and Q_t2. Boost cap provides the gate charge to the high side FET during the high-side turn-on and is recharged when the bottom switch turns on. Hence, the capacitance value of the boost capacitor must be selected such that the voltage drop during the discharge is under acceptable limits. Choosing a very large capacitor value slows down the charging of the capacitor, and it might not completely charge in the minimum off-time of the top switch.

Select the boost diode based on the average gate-drive current and blocking voltage for the diode. The maximum blocking voltage for the diode must be high enough to block the maximum drain-to-source voltage for the FET. A fast reverse-recovery diode would prevent any current being sourced into the bias supply from drain-to-source voltage. For the MAX25431, the gate drive is powered by the V_CC regulator, which is 5V (typ).

Since boost capacitor provides the gate charge to top switch, the value of boost capacitance needed for less than a Δ_VBOOST ripple on boost capacitor can be written as:

C_{BOOST} \geq \frac{Q_{G}}{∆ V_{BOOST}}

Average gate-drive current through the diode can be calculated as:

I_{G} = Q_{g} \times f_{SW}

where Q_g = Total gate charge of the top MOSFET.

Start the design by setting the output voltage and switching frequency for the controller. Selecting R_FB2 = 10kΩ gives R_FB1 = 86kΩ, to set the output voltage to 12V. Connect a 13kΩ resistor between the FSW and AGND pins to set the switching frequency to 2MHz.

Selecting the Current-Sense Resistor

The input current-sense resistor sets the peak current limit of the converter. For a 5A (max) output current, the maximum input current is 20A. The peak current-limit threshold for the input current sense is 50mV (typ).

I_{LPEAK} = \frac{V_{O} \times I_{O}}{V_{SUPMIN}} + \frac{V_{SUPMIN} \times (1 - \frac{V_{SUPMIN}}{V_{O}})}{L \times f_{SW} \times 2} = 15.55

Hence, the input current-sense resistor must be selected such that the peak current limit is higher than the peak input current. For this application:

Select

R_{CS 1} = 3 mΩ; I_{LIM} = \frac{50 mV}{3 mΩ} = 16.67 A

The runaway current limit is set by the output currentsense resistor at a 75mV threshold. Select the output current-sense resistor such that the runaway current limit is higher than the peak current limit by some safe margin:

Select R_CS2=3mΩ;

I_{LMIN - RUNAWAY} = \frac{75 mV}{2 mΩ} = 25 A

Table 1. Design Example
PARAMETERS	VALUE
V_OUT	12
f_SW	2MHz
V_SUP	4V–18V
I_OUT	5A (max)

Inductor Design

Start inductor selection by assuming 30% current ripple in buck mode, which gives the inductor to be:

L_{BUCK} > \frac{(V_{SUPMAX} - V_{O}) \times V_{O}}{f_{SW} \times I_{L_MAX} \times % ∆ I_{RIPPLE} \times V_{SUPMAX}} = 1.33 μH

For a converter operating in boost mode, the inductor selection determines the RHP frequency and hence the stability of converter in deep boost mode. Calculate the RHP zero frequency in deep boost mode using the calculated inductor value:

ω_{RHP} = \frac{R_{L} \times {(1 - D)}^{2}}{L \times 2 π} = 31.93 kHz

With RHP zero at 31.93kHz, the loop cutoff frequency for a stable operation must be less than 1/4 of the RHP zero frequency in deep boost mode.

Select L = 1.2μH, ω_rhp = 35.4kHz

Select a 1.2μH inductor to give a target crossover frequency of approximately 9kHz. Inductor current ripple in boost mode can now be verified using this value of the inductor:

%ΔI_{RIPPLE(BOOST)}>

\frac{(1 - \frac{V_{SUPMIN}}{V_{O}}) \times V_{SUP (MIN)}}{f_{SW} \times I_{L (MAX)} \times L} \times 100 = 7.4 %

Output Capacitor Design

C_{OUT} \geq \frac{L \times ∆ {I_{LSTEP}}^{2}}{2 \times V_{SUP_MIN} \times D_{MAX} \times V_{UNDER}} + \frac{(∆ I_{LSTEP} \times ∆ t_{DELAY})}{V_{UNDER}} = 88.54 μF

Slope Compensation

Select the slope-compensation resistor to have a worst-case Q_p value of approximately 0.6. Since the slope compensation is fixed once the resistor is selected, design for maximum input voltage:

For Q_p = 0.6, m_c = 3.12

S_{n} = \frac{(V_{SUP (MAX)} - V_{O}) \times G_{CS}}{L} = 3.525 \times 10^{5} V / s

For m_c = 3.12,

S_e = 7.05 x 10⁵V/s, V_p2p (external slope) = 360mV

Calculate R_SLOPE to achieve the desired peak-to-peak voltage for the external compensation as calculated above.

Select R_SLOPE = 18kΩ for V_P2P ≅ 390mV

Error-Amplifier Compensation Design

Start the compensator design by calculating the critical frequencies for the boost power stage at the minimum input voltage and maximum load.

f_{PBOOST} = \frac{2}{2 π \times R_{L} \times C_{OUT}} = 1.3 kHz

$f_{ESR} = \frac{1}{2 π \times R_{C} \times C_{OUT}} = 531 kHz$ $f_{RHP} = \frac{R_{L} \times {(1 - D)}^{2}}{2 π \times L} = 35 kHz$

With RHP zero at 35kHz, a target bandwidth for the closed-loop converter close to 9kHz is selected. The zero of the error amplifier must be placed well below the bandwidth to give enough phase boost at the crossover frequency. Typically, the zero is placed close to the low-frequency pole. In such a case, resistor (R_ZERO) of the compensation can be calculated using equation below:

R_{ZERO} = 2 {πf}_{BW} \times \frac{G_{CS} \times C_{OUT}}{gm \times (1 - D_{BOOST})} \times \frac{(R_{BOT} + R_{TOP})}{R_{BOT}}

Choosing:

f_BW = 9kHz; gives R_ZERO = 16kΩ

with:

f_ZCOMP=1.5 kHz;

C_{ZERO} = \frac{1}{R_{ZERO} \times 2 π \times f_{ZCOMP}} = 6.58 nF

C_pole decides the location of high-frequency pole. Select the high-frequency pole location higher than the bandwidth in buck mode so that it does not affect the phase margin and helps attenuate any high-frequency noises.

C_{POLE} = \frac{1}{R_{ZERO} \times 2 π f_{p 2 COMP}}

For f_p2COMP= 200kHz, C_POLE = 50pF

Select R_ZERO = 16kΩ, C_ZERO = 5.6nF and C_POLE = 50pF

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching power losses and clean, stable operation. Use a multilayer board whenever possible for better noise immunity. Follow the guidelines below for a good PCB layout:

Arrange the high-power components in a compact layout away from the sensitive signals such as the current-sense and gate-drive signals, etc., to avoid stray noise pickup.
Place the input capacitor and the input current-sense resistor close to the input MOSFETs (Qt1 and Qb1) to make a small input current AC loop. High-frequency AC currents flow in this loop in buck mode (Figure 3) and a small loop helps with the EMI and noise performance. Add high-frequency decoupling caps to improve the high-frequency performance.
Place the output capacitor and the output current-sense resistor close to the output MOSFETs (Q_t2 and Q_b2) to make a small output-current AC loop. High-frequency AC currents flow in this loop in boost mode (Figure 3) and a small loop helps with the EMI and noise performance. Add high-frequency decoupling caps to improve the high-frequency performance.
The switching nodes (LX1 and LX2) carry high-frequency, high-current switching signals. Make LX1 and LX2 areas small to reduce parasitic inductance in the switching nodes. Since high currents flow through these nodes, a compromise must be made between thermal dissipation and noise mitigation.
Use a Kelvin sense connection for the current-sense resistors and route the sense traces close to each other to ensure a balanced measurement of the differential signal. Route these traces away from other noisy traces.
Use short and thick traces for gate connection to avoid any gate ringing.
Using internal PCB layers as a ground plane helps to improve the EMI functionality. A solid ground plane like the inner layer act as a shield against radiated noise. Have multiple vias spread around the board, especially near the ground connections, to have better overall ground connection.
Connect the PGND and AGND pins directly to the exposed pad under the IC. This ensures the shortest connection path between AGND and PGND.
Solder the exposed pad to a large copper-plane area under the device. To effectively use this copper area as a heat exchanger between the PCB and ambient, expose the copper area on the top and bottom side. Add a few small vias or one large via on the copper pad for efficient heat transfer.
Keep the bias capacitor (C_BIAS) close to the device to reduce the bias current loop. This helps to reduce noise on the bias for smoother operation.

Figure 3. Recommended PCB Layout for the MAX25431.