| Package Code | TD1233+2C |
| Outline Number | 21-0664 |
| Land Pattern Number | 90-0397 |
| THERMAL RESISTANCE, FOUR-LAYER BOARD | |
| Junction-to-Ambient (θJA) | 41°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 8.5°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX25231ATCD%2FV%2B
data-opMAX25231ATCD%2FV%2BT
data-opMAX25231ATCB%2FV%2BT
data-opMAX25231ATCB%2FV%2B
data-opMAX25231ATCA%2FV%2B
data-opMAX25231ATCA%2FV%2BT
Spread-Spectrum Enable. Connect logic-high to enable spread spectrum of internal oscillator or logic-low to disable spread spectrum. This pin has a 1MΩ internal pulldown.High-Voltage-Compatible Enable Input. If this pin is low, the part is off.Bootstrap Pin for HS Driver. It is recommended to use 0.1μF from BST to LX.Supply Input. Connect a 4.7μF ceramic capacitor from SUP to PGND.Buck Switching Node. High impedance when part is off. Connect a 4.7μH inductor between LX and OUT.Power Ground. Ground return path for all high-current/high-frequency noisy signals.Analog Ground. Ground return path for all ‘quiet’ signals.Feedback Pin. Connect a resistor-divider from OUT to FB to ground for external adjustment of the output voltage (MAX25231ATCD only). Connect to bias for internal fixed voltage configurations.Buck Regulator Output-Voltage-Sense Input. Bypass OUT to PGND with 22μF ceramic capacitor.5V Internal BIAS Supply. Connect a 1μF (min) ceramic capacitor to AGND.Sync Input. If connected to ground or open, skip-mode operation is enabled under light loads; if connected to BIAS, forced-PWM mode is enabled. This pin has a 1MΩ internal pulldown.Open-Drain Reset Output. External pullup required.Exposed Pad. EP must be connected to ground plane on PCB, but is not a current-carrying path and is only needed for thermal transfer.