Applications Information

MAX25231ATCA and MAX25231ATCB are configured with a fixed output voltage.

MAX25231ATCD is configured with an adjustable output voltage between 3V and 10V. Connect a resistive divider from output (OUT) to FB to AGND as the following figure. Select R_FB2 (FB to AGND resistor) less than or equal to 500kΩ. Calculate R_FB1 (OUT to FB resistor) with the following equation:

R_FB1 = R_FB2 [(V_OUT/V_FB)-1)]

where V_FB = 1V.

The design is optimized with 4.7μH inductor for all input and output voltage conditions. The nominal standard value selected should be within ±50% of 4.7μH.

A low-ESR ceramic input capacitor of 4.7μF is recommended for proper device operation. This value can be adjusted based on application input-voltage ripple requirements.

The discontinuous input current of the buck converter causes large input ripple current. The switching frequency, peak inductor current, and the allowable peak-to-peak input-voltage ripple dictate the input-capacitance requirement. Increasing the switching frequency or the inductor value lowers the peak-to-average current ratio, yielding a lower input-capacitance requirement.

The input ripple is primarily composed of ΔV_Q (caused by the capacitor discharge) and ΔV_ESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of ΔV_Q and ΔV_ESR. Assume that input-voltage ripple from the ESR and the capacitor discharge is equal to 50% each. The following equations show the ESR and capacitor requirement for a target voltage ripple at the input:

Equation 1:

$\mathrm{ESR}=\frac{∆V_{\mathrm{ESR}}}{I_{\mathrm{OUT}}+(∆I_{P-P}/2)}$

$C_{\mathrm{IN}}=\frac{I_{\mathrm{OUT}}\times D(1-D)}{∆\mathrm{VQ}\times f_{\mathrm{SW}}}$

where:

$∆I_{P-P}=\frac{(V_{\mathrm{IN}}-V_{\mathrm{OUT}})\times V_{\mathrm{OUT}}}{V_{\mathrm{IN}}\times f_{\mathrm{SW}}\times L}$

and:

$D=\frac{V_{\mathrm{OUT}}}{V_{\mathrm{IN}}}$

where I_OUT is the output current, D is the duty cycle, and f_SW is the switching frequency. Use additional input capacitance at lower input voltages to avoid possible undershoot below the UVLO threshold during transient loading.

For optimal phase margin (> 70 deg, typ) with internal fixed-voltage options, a 22μF output capacitor is recommended. A lower output capacitor can be used at the expense of lower phase margin. For all other designs, a minimum 10μF output capacitor is required. Additional output capacitance may be needed based on application-specific output-voltage ripple requirements. If the total output capacitance required is > 70μF, contact the factory for an optimized solution.

The allowable output-voltage ripple and the maximum deviation of the output voltage during step-load currents determine the output capacitance and its ESR. The output ripple comprises ΔV_Q (caused by the capacitor discharge) and ΔV_ESR (caused by the ESR of the output capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic capacitors, the entire output ripple is contributed by ΔV_ESR. Use the ESR_OUT equation to calculate the ESR requirement and choose the capacitor accordingly. If using ceramic capacitors, assume the contribution to the output ripple voltage from the ESR and the capacitor discharge to be equal. The following equations show the output capacitance and ESR requirement for a specified output-voltage ripple.

Equation 2:

$\mathrm{ESR}=\frac{∆V_{\mathrm{ESR}}}{∆I_{P-P}}$

$C_{\mathrm{OUT}}=\frac{∆I_{P-P}}{8\times ∆V_Q\times f_{\mathrm{SW}}}$

where:

$∆I_{P-P}=\frac{(V_{\mathrm{IN}}-V_{\mathrm{OUT}})\times V_{\mathrm{OUT}}}{V_{\mathrm{IN}}\times f_{\mathrm{SW}}\times L}$

and:

$V_{\mathrm{OUT\_RIPPLE}}=∆V_{\mathrm{ESR}}+∆V_Q$

ΔI_P-P is the peak-to-peak inductor current as calculated above, and f_SW is the converter’s switching frequency. The allowable deviation of the output voltage during fast transient loads also determines the output capacitance and its ESR. The output capacitor supplies the step-load current until the converter responds with a greater duty cycle. The response time (t_RESPONSE) depends on the closed-loop bandwidth of the converter. The high switching frequency of the devices allows for a higher closed-loop bandwidth, thus reducing t_RESPONSE and the output-capacitance requirement. The resistive drop across the output capacitor’s ESR and the capacitor discharge causes a voltage droop during a step load. Use a combination of low-ESR tantalum and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output-voltage deviations below the tolerable limits of the electronics being powered. When using a ceramic capacitor, assume an 80% and 20% contribution from the output-capacitance discharge and the ESR drop, respectively. Use the following equations to calculate the required ESR and capacitance value:

Equation 3:

${\mathrm{ESR}}_{\mathrm{OUT}}=\frac{∆V_{\mathrm{ESR}}}{I_{\mathrm{STEP}}}$

$C_{\mathrm{OUT}}=\frac{I_{\mathrm{STEP}}\times t_{\mathrm{RESPONSE}}}{∆V_Q}$

where I_STEP is the load step and t_RESPONSE is the response time of the converter. The converter response time depends on the control-loop bandwidth.

Careful PCB layout is critical to achieve low switching power losses and clean, stable operation. Use a multilayer board wherever possible for better noise immunity. Follow the guidelines below for a good PCB layout:

1. The input capacitor (4.7μF, see Circuit1 - Fixed Output Typical Application Circuit) should be placed right next to the SUP pin. Since the MAX25231 operates at 2.1MHz switching frequency, this placement is critical for effective decoupling of high-frequency noise from the SUP pins.
2. Solder the exposed pad to a large copper-plane area under the device. To effectively use this copper area  as a heat exchanger between the PCB and ambient, expose the copper area on the top and bottom side. Add a few small vias or one large via on the copper pad for efficient heat transfer. Connect the exposed pad to PGND, ideally at the return terminal of the output capacitor.
3. Isolate the power components and high-current paths from sensitive analog circuitry.
4. Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation.
5. Connect PGND and AGND together, preferably at the return terminal of the output capacitor. Do not connect them anywhere else.
6. Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper PCB to enhance full-load efficiency and power-dissipation capability.
7. Route high-speed switching nodes away from sensitive analog areas. Use internal PCB layers as PGND to act as EMI shields to keep radiated noise away from the device and analog bypass capacitor.