Detailed Description

The MAX25222/MAX25222C are 4-channel TFT-LCD power ICs that provide symmetrical positive AVDD and negative NAVDD supplies as well as VG_ON and V_GOFF gate supplies. In addition, a VCOM buffer with output voltage range above and below ground and a temperature-measurement block are integrated.

These devices contain non-volatile memory so that the values of all outputs can be calibrated for the lifetime of the device.

Programming is carried out using the built-in I²C interface, which can also be used to read back diagnostic information. Operation in stand-alone mode is also possible.

The temperature-sensor interface block determines the temperature by measuring the voltage on the R_REF pin when a temperature-sensitive component, such as an NTC, is connected to TEMP. The VCOM output voltage can be adjusted as a function of the measured temperature.

When power is applied, the MAX25222/MAX25222C are in low-quiescent-current mode until the EN pin is taken high. When EN is taken high (if the device supply voltage on IN exceeds the undervoltage lockout voltage of 2.5V), the 1.8V regulator is turned on and the device is functional after a delay of 1ms. Subsequent operation depends on the device configuration and type as shown in Table 1.

If the non-volatile memory has been written to previously and the ADD pin is open (stand-alone mode), the stored values are read and the outputs are turned on in the programmed sequence when the EN pin is taken high. Otherwise, the device powers up with the default voltages of 6.8V (AVDD), 12V (VG_ON), and -10V (VG_OFF).

Alternatively, when I²C is used, all values can be programmed and the outputs turned on using the START bit in the REG_CTRL register. The values can subsequently be stored in non-volatile memory using the burn_otp command, if required.

If at any time the internal 1.8V regulator is out of range, the v18oor bit is set in register FAULT2 and the FLTB pin is asserted low, assuming the device is being used in I²C mode. No other action is taken unless the V18 voltage is below its undervoltage lockout level.

The source-driver power supplies consist of a boost converter with output switch and an inverting buck-boost converter that generate up to +10.5V maximum and down to -10.5V minimum, respectively, and can deliver up to 200mA on the positive regulator and -200 mA on the negative regulator. The positive source-driver power supply’s regulation voltage (AVDD) is set by writing the avdd[5:0] value in the AVDD_SET register using the I²C interface, and can be programmed into non-volatile memory. The default AVDD output voltage is 6.8V.

The negative source-driver supply voltage (NAVDD) is automatically tightly regulated to -AVDD within ±34mV. NAVDD cannot be adjusted independently of AVDD.

The AVDD boost converter is a current-mode converter with two internal switches and internal compensation. The direct output of the converter is HVINP while AVDD is a switched-output version. The NAVDD converter is a current-mode converter with one internal switch, an external diode and internal compensation.

The positive gate-driver power supply (VG_ON) is a regulated charge-pump tripler and generates up to +20.2V. Note also that the maximum output voltage is 3 x AVDD - R_ONTOTAL x I_VGON x K, where R_ONTOTAL is typically 30Ω and K is a factor 0.75. In cases where a doubler charge pump is sufficient, set the cp_2stage bit and leave pins FC1- and FC1+ unconnected in order to increase efficiency.

The negative gate-driver power supply (VG_OFF) generates a maximum negative voltage of -18.2V and requires external diodes and capacitors. The VG_ON and VG_OFF blocks switch at the same frequency as the AVDD and NAVDD converters.

Both supplies are capable of output currents up to 15mA, assuming sufficient headroom. The VG_ON and VG_OFF regulation voltages are set by writing the vgon[5:0] and vgoff[5:0] values in the register map using the I²C interface, and can be stored in the non-volatile section of the register map.

The power-on and power-off sequences are controlled by the seq_set[2:0] bits in the VCOM_L register. The setting should be written before the sequence is to be executed and should not be changed during the turn-on or turn-off sequences. The sequence options are as follows:

The times in Table 2 are determined by the delayt1, delayt2 and delayt3 settings in the DELAY-VCOM_LSB register. The fastest power-up is obtained by setting the delays to 0.

The output voltages are not monitored during off sequencing; each output is turned off in turn using the programmed delays. When the delays are set to zero, outputs are turned off in sequence with 1ms delays .A sequence can be stored in non-volatile memory by writing to the burn_otp_reg register.

The V18 linear regulator is powered down 200ms after the power-down sequence is complete. After this time, the device is in shut-down mode and can be restarted by setting the EN input high.

The VCOM output voltage is programmed using I²C to a value between -2.49V and +1V. The 9-bit value can also be stored in non-volatile memory. The most-significant bits of the VCOM voltage setting are in the VCOM25 register while the least-significant bit is the vcom25_0 bit in the DELAY-DELAYVCOM_LSB register.

The VCOM buffer can output peak currents up to ±120mA. If the VCOM output voltage deviates from the set value by more than 0.25V, a VCOM fault is detected and flagged with the vcom_flt bit in the FAULT2 register. When this fault is detected, the VCOM buffer continues to function—it is not automatically disabled. Note that a fault condition can lead to high power dissipation in the VCOM buffer and could lead to thermal shutdown of the entire device. If the VCOM buffer is continuously in current limit for more than the time set by tfault[1:0], it is disabled together with the AVDD, NAVDD, VG_H and VG_L outputs to avoid damage to the IC. Also in this case the vcom_flt bit is set.

The maximum capacitive load on the VCOM output is 10nF. If higher capacitance loads are used, a series resistor should be employed to maintain stability.

To calculate the value to write to the VCOM25 register use the following equation:

$\mathrm{VCOM}25=\frac{V_{\mathrm{COM}}+2.49}{0.00683}$

The correspondence between the VCOM set value and the VCOM voltage is shown in Table 3.

The VCOM output voltage can be compensated for temperature changes using a temperature-sensitive component (e.g. an NTC thermistor) connected to the TEMP input or an internal temperature sensor. Select the sensor to be used with the int_sensor bit in the CONFIG register (the default configuration is to use the external sensor). The TEMP pin is forced to 625mV and the current drawn from it is mirrored on the R_REF pin. The voltage generated due to the resistor on R_REF is fed to the internal 8-bit ADC, which has a reference voltage of 1.25V. The input to the ADC is therefore as follows:

$V_{\mathrm{ADC}}=\frac{0.625\times R_{\mathrm{RREF}}}{R_{\mathrm{TEMP}}}$

With reference to Figure 2: $R_{\mathrm{TEMP}}=(R_{\mathrm{NTC}}||R1)+R2$

The highly non-linear NTC characteristic can be modified depending on which temperature (cold, room, or hot) necessitates the highest resolution. As an example in Figure 2, a reference resistor is connected to R_REF while a combination of the NTC and two low-TC resistors R1 and R2 are connected to TEMP. In this way, an ADC reading that is steeper at higher temperatures is obtained, enhancing the resolution of the ADC there. When temperature compensation is enabled, the value of the voltage on the R_REF pin is available in the TEMP (0x01) register.

Temperature compensation is enabled by setting the T_comp_en bit in the DELAY-VCOM_LSB register. When T_comp_en is high, the voltage on the R_REF pin is measured and the VCOM output voltage is updated at a rate of 1Hz. At start-up, even with temperature compensation enabled, there is a delay before compensation becomes active due to the time needed to sample the temperature. For this reason, the device always starts up with the VCOM25 voltage value on VCOM.

The VCOM value at +25°C is the value written in the VCOM25 register together with the LSB from DELAY-VCOM_LSB register. This value serves as the reference for all other VCOM values. The 5-bit values in the VCOM_L, and VCOM_H1 registers represent the change in VCOM from the VCOM25 value at the temperature represented by an ADC reading of VTEMP_L and VTEMP_H1. The value in the VCOM_H2 register represents the positive shift in VCOM from VCOM_H1. The VCOM_L value represents a negative shift in VCOM while VCOM_H1 and VCOM_H2 represent positive shifts.

The internal temperature sensor senses the junction temperature of the IC which may be significantly different from the ambient temperature. To use the internal sensor, set the int_sensor bit in the CONFIG register to 1. The internal temperature sensor has a temperature coefficient of 2mV/°C and a nominal output voltage of 620mV at +25°C.

When the internal temperature sensor is selected, it is connected directly to the ADC input.

The reaction to faults is dependent on whether the device is in I²C or stand-alone mode.

In I²C mode, the following faults, if not masked, cause the FLTB pin to assert low: avdd_uv, navdd_uv, vgon_uv, vgoff_uv, vcom_flt, nv_flt, th_shdn, vin_uvlo, and par_err. The th_warn fault is masked by default and must be explicitly enabled using the th_warn_mask bit.

When the ADD pin is left floating (I²C interface not used), the FLTB pin outputs a pulse train of varying duty cycle depending on the detected fault as shown in Table 4.

The frequency at the FLTB pin is 1kHz when indicating a fault. If multiple faults are present, the highest-priority fault is indicated. The Table 4 list is in order of priority with the highest priority listed last.

When an undervoltage is detected on any of the AVDD, NAVDD, VG_ON, or VG_OFF outputs, all of the outputs are turned off and the appropriate fault bit is set in the FAULT1 register. At the same time, the FLTB pin asserts low. Depending on the setting of the tretry[1:0] bits, the subsequent behavior of the device is as follows:

• tretry = 01, 10 or 11: After 0.95s or 1.9s a retry is performed where all outputs are turned on in the appropriate sequence. If the fault is still present, the output will be disabled again after tfault[1:0]. A total of three retries are performed, after which no further retry attempts are performed (the device can be restarted by toggling power or the EN pin or by using the RESTART command). If tretry = 11 retries continue until the fault is removed and normal function can resume.
• tretry = 00: No retry is attempted (the device can be restarted by toggling power or the EN pin or by using the RESTART command).

If a short-circuit is encountered during start-up, device operation is halted, all outputs are disabled, and the subsequent behavior depends on the setting of retry[1:0] as described above. The short-circuit checks on VG_ON and VG_OFF are enabled 1ms after the pins are enabled. The C version does not have short-circuit checks on VG_ON and VG_OFF.

During retry, faults are no longer monitored and the fault or faults which caused retry are indicated using the corresponding fault bits. During retry, the FLTB pin asserts low unless the fault which caused the retry is masked.

The other faults detected by the MAX25222/MAX25222C are as follows:

• FLTB pin stuck low or high. This is detected when the voltage on FLTB does not agree with the expected value. It is indicated by the flt_flt bit in the FLTMASK2 register.
• Bandgap reference out of range. The two internal references are constantly compared; if they differ by more than ±11%, both the hvinp_uv (FAULT2 register) and hvinp_ov (FAULT1 register) bits are asserted simultaneously.
• Communication parity error (when enabled by setting the par_en bit in the REG_CTRL register). This error causes the par_err bit in register FAULT2 to be asserted.
• VCOM DAC fault. This bit in the FLTMSK2 register is the direct output of the VCOM DAC midway comparator used to detect a stuck DAC output. This bit does not cause FLTB to assert low and thus must be polled by the user. It is not latched, but instead reflects the output of the comparator directly.

When the junction temperature reaches 125°C, the thermal warning bit is set. The device takes no further action.

If the device junction temperature reaches 160°C, all outputs are turned off immediately. When the junction temperature drops by 15°C, the outputs are re-enabled using the stored sequence.

The MAX25222/MAX25222C include six blocks of one-time-programmable memory (the number of writes performed so far can be read from nv_count[2:0] in the REG_CTRL register). The user can store the block of volatile registers from 0x07 to 0x15 in non-volatile memory which is in turn mapped to register locations 0x17 to 0x25. Note that before the non-volatile memory has been programmed, a read from the locations 0x17 to 0x25 yields the result 0xFF.

The contents of the non-volatile memory are protected by a single-error correction/double-error detection (SECDED) redundant code while data transfer from non-volatile memory to registers 0x07 to 0x15 is protected by a parity check. If the parity check fails, a retry is performed two times. If all three attempts are unsuccessful, the device does not start up, the nv_flt bit is set, and the FLTB pin is asserted low. If the SECDED check fails, the device does not start up, the nv_flt bit is set, and the FLTB pin is asserted low.

If there are no errors, the outputs are turned on with the stored values and in the stored sequence.

To store the contents of registers 0x07 to 0x15 to non-volatile memory a voltage source of 8.5V ±2% capable of supplying more than 25mA should be connected to the V_PROG pin. When the V_PROG voltage is stable an I²C NV write command can be performed by writing to the burn_otp_reg register. If the NV write is unsuccessful (because the V_PROG voltage was out of range or because of a general memory error) the nv_flt bit is set, FLTB pin goes low. After an NV write command is executed, the nv_flt bit should be checked. If nv_flt is high another NV write can be attempted.

Connect V_PROG to GND if non-volatile memory is not used.

Ensure that temperature compensation is disabled when programming VCOM.

When the refresh bit in register CONFIG is set, the device reads from the non-volatile registers at intervals of 1s and writes the data into the corresponding volatile registers. This avoids the effect of possible corruption of the volatile registers. Auto-refresh reads are subject to error correction in the same way as the initial read after device power-up.

When programming the non-volatile memory, the auto-refresh function should be enabled immediately before performing the burn_otp_reg write. See the section Using the NV Memory in Applications Information.

The BURN and REBOOT commands are used to store the contents of registers 0x07 to 0x15 in non-volatile memory or to fetch the contents of non-volatile memory and load them into registers 0x07 to 0x15, respectively. The RESTART command is used to restart the device from a latched-fault mode. When a RESTART command is performed, all fault bits are cleared.

A BURN command is performed by writing to register address 0x78 (burn_otp_reg).

A REBOOT command is performed by writing to register address 0x79 (reboot_otp_reg).

A RESTART command is performed by writing to register address 0x7A (soft_restart).

When parity checking is enabled and one of these user commands is sent to the device, the third byte should be such as to have even parity over the 3 bytes sent.

The MAX25222/MAX25222C include an I²C, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 400kHz. The master, typically a microcontroller, generates SCL and initiates data transfer on the bus.

The Slave ID of the MAX25222/MAX25222C depends on the connection of the ADD pin according to Table 4.

A master device communicates with the MAX25222/MAX25222C by transmitting the correct Slave ID with appended R/W bit, followed by the register address and data word (for a write transaction only). Each transmit sequence is framed by a START (S) or Repeated START (Sr) condition, and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.

The IC's SDA line operates as both an input and an open-drain output. A pullup resistor greater than 1kΩ is required on the SDA bus. In general, the resistor should be selected as a function of bus capacitance such that the rise time on the bus is not greater than 120ns. The IC's SCL line operates as an input only. A pullup resistor greater than 1kΩ is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. In general, for the SCL-line resistor selection, the same recommendations as for SDA apply. Series resistors in line with SDA and SCL are optional. The SCL and SDA inputs suppress noise spikes to assure proper device operation even on a noisy bus.

* On the MAX25222C, writing to the device is not possible when ADD is connected to V18.

Even parity checking for write transactions can be enabled by setting the par_en bit in REG_CTRL to 1. The parity bit is the most-significant bit of the register address byte and should be set to attain even parity. The parity check is performed over all 3 bytes received by the device: the slave address, the register address, and the data payload. Burst-mode write is not supported when parity checking is enabled; a complete I²C transaction is needed to write to each single register. When a parity bit error is detected the par_err bit is set, the I²C interface issues a NACK and no write is performed.

When writing any of the BURN, REBOOT, and RESTART commands, parity must be adjusted by changing the third or payload byte; the command byte must not be changed.