Applications Information

Three key inductor parameters must be specified for operation with the device: Inductance value (L), inductor saturation current (I_SAT), and DC resistance (R_DC). Use a 2.2μH inductor when the boost converter operates at 2.1MHz and 10μH at 420kHz.

The inductor’s saturation rating must exceed the maximum current limit of 2.3A.

The primary criterion for selecting the output filter capacitor is low effective series resistance (ESR). The product of the peak inductor current and the output filter capacitor’s ESR determine the amplitude of the high-frequency ripple seen on the output voltage. For stability, the boost output-filter capacitor should have a value of 10μF or greater when using 2.1MHz switching.

To avoid a large drop on HVINP when AVDD is enabled, the capacitance on the HVINP node should be at least three times larger than that on AVDD.

Sufficient input capacitance must be used to avoid input voltage drop when transients are encountered on the AVDD or NAVDD outputs and when the AVDD switch is closed. If the IN voltage drops below 2.57V, the device is likely to reset so input capacitance must prevent this. The total value of capacitance depends on the expected transients and the series resistance in the IN connection. A good starting point is a total input capacitance of 2 x 22μF ceramic capacitors in parallel with 2 x 10μF ceramic capacitors. Depending on the particular application circumstances more or less capacitance may be needed.

Input capacitance requirements are significantly relaxed when an input voltage of 5V is used.

The AVDD output voltage is set by writing a 6-bit value to the AVDD_SET register.

The NAVDD converter outputs a negative voltage whose absolute value is the same as AVDD.

Three key inductor parameters must be specified for operation with the device: inductance value (L), inductor saturation current (I_SAT), and DC resistance (R_DC). Use a 2.2μH inductor when the converter operates at 2.1MHz and 10μH at 420kHz.

The inductor's saturation current rating must exceed the maximum current limit of 2.25A.

The primary criterion for selecting the output filter capacitor is low ESR and capacitance value, as the NAVDD capacitor provides the load current when the internal switch is on. The voltage ripple on the NAVDD output has two components:

1. Ripple to due ESR which is the product of the peak inductor current and the output filter capacitor’s ESR
2. Ripple due to bulk capacitance that can be determined as follows.

${\mathrm{\Delta V}}_{\mathrm{BULK}}=\frac{I_{\mathrm{NAVDD}}\times {\displaystyle \frac{D}{f_{\mathrm{SW}}}}}{C_{\mathrm{NAVDD}}}$

For stability, the NAVDD output capacitor should have a value of 10μF or greater when using 2.1MHz switching frequency.

The internal positive charge pump can output a voltage approximately three times AVDD. If a voltage of twice the HVINP voltage is sufficient leave the FC1+ and FC1- pins unconnected and set the cp_2stage bit.

For V_GOFF, the number of charge-pump stages should be chosen to ensure sufficient output voltage while maintaining the VG_OFF voltage within its permitted operating range.

The VG_ON output voltage is set by writing a 6-bit value to the vgon[5:0] field in the VG_ON register.

The VG_OFF voltage is set by writing a 6-bit value to the vgoff[5:0] field in the VG_OFF register.

Assume that an NTC with 10kΩ resistance at 25°C is connected from TEMP to GND and that the R_REF resistor is of value 2400Ω. At various temperatures, the following voltages will be observed on R_REF and the ADC measurement result will be as follows:

The rightmost column of the previous table indicates the desired VCOM output voltage at each temperature, which will be the inflection points in the temperature compensation curve. The following values are written to the relevant registers (remembering that each LSB of the VCOM setting represents 6.83mV):

With these settings, the VCOM output voltage at 25°C is -1V, while at the temperature represented by 13mV at the R_REF pin the VCOM voltage decreases to -1.09V as set by the VCOM_L register. Similarly, the VCOM_H1 and VCOM_H2 values are output on VCOM when the TEMP voltage is 500mV and 1V, respectively. In between these values the device interpolates the correct VCOM voltage value with a resolution of 6.83mV. The complete curve is shown in Figure 4.

When setting the values VTEMP_xx and VCOM_xx, it is important to avoid values which can cause wraparound in the temperature compensation algorithm thus possibly leading to sudden changes in the value of VCOM.

Follow the sequence below to perform non-volatile programming of the device when the auto-refresh function is not used:

1. Apply a voltage between 3.3V and 5V to the IN and INN pins with the device in I²C mode
2. Write the desired values to be stored in OTP to the registers from 0x07 to 0x15
3. Apply 8.5V to V_PROG
4. Optionally wait to ensure the 8.5V at V_PROG is stable
5. Send burn_otp_reg (write any value to 0x78) command. If parity is enabled ensure the overall parity is even by altering the final byte if necessary.
6. Wait 20ms
7. If the nv_flt bit is 0, the write was successful, go to next step. If nv_flt = 1, perform re-try (steps 5,6).

8. Send reboot_otp (write any value to 0x79) command.

Special care is required when performing non-volatile programming with the auto-refresh feature enabled. In such cases follow the sequence below when at least one calibration has already been performed:

1. Apply a voltage between 3.3V and 5V to the IN and INN pins

2. Write the desired values to be stored in NV memory to the registers from 0x07 to 0x15 (keep auto-refresh bit disabled until here)

3. Enable the auto-refresh feature

4. Start polling one of the registers from 0x07 to 0x15 which has changed its value until that value gets refreshed to the older one (auto-refresh is active)

5. The following steps from #6 to #10 must be completed within 1s

6. Write the desired values to be stored in OTP to the registers from 0x07 to 0x15 (including auto-refresh bit).

7. Apply 8.5V to V_PROG

8. Optionally wait to ensure the 8.5V at V_PROG is stable

9. Send burn_otp_reg (write any value to 0x78) command. If parity is enabled ensure the overall parity is even by altering the final byte if necessary

10. Wait 20ms

11. If the nv_flt bit is 0, the write was successful, go to next step. If nv_flt = 1, perform retry from step 2.

12. Send reboot_otp (write any value to 0x79) command

The non-volatile memory can be written to a total of six times.

The MAX25222/MAX25222C include high-frequency switching converters to generate the voltages for TFT-LCDs. Take proper care while laying out the circuit board to ensure correct operation. The switching-converter portions of the circuit have nodes with very fast voltage changes that could lead to undesirable effects on the sensitive parts of the circuit as well as electromagnetic interference (EMI). Follow the guidelines below to reduce noise as much as possible:

• Connect the bypass capacitors on IN and INN as close as possible to the device and connect the capacitor ground to the analog ground plane using vias close to the capacitor terminal. Ensure that the power connection to IN and INN uses a very wide trace or complete board layer to avoid input undervoltage problems.
• Connect the GND pin of the device to the analog ground plane using a via close to GND. Lay the analog ground plane on the inner layer, preferably next to the top layer. Use the analog ground plane to cover the entire area under critical signal components for the power converter.
• Have a power-ground plane for the switching-converter power circuit under the power components (i.e., input filter capacitor, output filter capacitor, inductor, MOSFET, rectifier diode, and current-sense resistor). Connect PGND to the power-ground plane closest to PGND. Connect all other ground connections to the power ground plane using vias close to the terminals.
• Minimize the copper area of all switching nodes to avoid EMI. Minimize the loop areas for the AVDD and NAVDD converters by placing all components close to the LXP and LXN pins. Place the input and output capacitor grounds close to each other. In the case of AVDD the input/output capacitor grounds should also connect directly to the PGND pin.
• Connect GND, CPGND and PGND at the exposed pad of the device.
• Refer to the evaluation kit (EV kit) data sheet for a sample layout.

In addition, when using an external NTC temperature sensor for temperature compensation connect the grounded end directly to the grounded end of the RREF resistor. This avoids possible differences in ground potential between different points on the circuit board.