Applications Information

Applications Information Design Procedure

Effective Input Voltage Range in the Buck Converter

Although the IC can operate from input supplies up to 60V/70V and regulate down to 0.7V, the minimum voltage conversion ratio for fixed frequency operation is limited by the minimum controllable on-time (t_ON,MIN):

\frac{V_{OUT}}{V_{IN}} > t_{ON, MIN} \times f_{SW}

where f_SW is the switching frequency. If the desired voltage conversion does not meet the above condition, pulse skipping occurs to maintain regulation. Decrease the switching frequency if constant switching frequency is required at higher input voltages.

The maximum voltage conversion ratio in buck mode of operation is limited by the maximum duty cycle (see Maximum Duty-Cycle Operation in Buck Mode). During low-drop operation, the IC reduces the switching frequency (f_SW) to ~80kHz.

The MAX25207 provides 100% duty cycle operation in bypass mode.

Setting the Output Voltage

Connect FB to BIAS to enable the fixed buck-controller output voltage (5V or 3.3V) set by a preset internal resistor voltage-divider connected between OUT and AGND. To externally adjust the output voltage between 0.7V and 20V, connect a resistor divider from the output (OUT) to FB to AGND.

\frac{R_{FB 2}}{R_{FB 1}} = (\frac{V_{OUT}}{V_{FB}}) - 1

where V_FB = 0.7V (typ) (see the Electrical Characteristics) and R_FB2, R_FB1 are top and bottom resistors in the feedback divider.

In skip mode, the IC regulates the valley of the output ripple.

Inductor Selection

The inductor is selected based on trade-off among size, cost, efficiency, and transient performance. A good starting point for inductance comes from targeting 30% peak-to-peak ripple current to average current ratio. The switching frequency, input voltage, output voltage, and target ripple are related to inductance as shown below:

L = \frac{(V_{IN} - V_{OUT}) \times D}{f_{SW} \times I_{OUT} \times 30 %}

where D (=V_OUT/V_IN) is the duty cycle. V_IN, V_OUT, and I_OUT are typical values (so that efficiency is optimum for typical conditions).

The inductance must satisfy the slope compensation criterion:

V_{SLOPE} f_{SW} > \frac{V_{OUT}}{2 \times L} A_{VCS} R_{CS}

where A_VCS is the current-sense amplifier gain (typical 13V/V). V_SLOPE is V_OUT dependent and is given by the following equation:

\begin{array}{lll} V_{SLOPE} & = 105 mV & for & 0 V < V_{OUT} \leq 3 V \\ = 210 mV & for & 3 V < V_{OUT} \leq 5.5 V \\ = 420 mV & for & 5.5 V < V_{OUT} \leq 9.7 V \\ = 525 mV & otherwise \end{array}

Peak Inductor Current

The peak inductor current is the sum of maximum load current and half of the peak-to-peak ripple current:

I_{PEAK} = I_{LOAD (MAX)} + \frac{∆ I_{L}}{2}

For the selected inductance value, the actual peak-to-peak inductor ripple current (ΔI_L) is calculated using the following equation:

∆ I_{L} = \frac{V_{OUT} (V_{IN} - V_{OUT})}{V_{IN} \times f_{SW} \times L}

The saturation current should be larger than I_PEAK or at least in a range where the inductance does not degrade significantly. The MOSFETs are required to handle the same peak current.

MOSFET Selection in Buck Converter

The high- and low-side n-channel MOSFETs should be selected to have sufficient voltage and current ratings. In addition, they should be able to handle the heat generated and temperature rise.

Both high- and low-side MOSFETs should be rated for maximum input voltage observed in the application. Provide additional margin for switch node ringing during switching.

Select MOSFETs with logic-level gate drive with guaranteed on-resistance specifications at V_GS = 4.5V. If BIAS switchover is enabled, the gate drive supply voltage follows V_OUT. In those cases, select MOSFETs to have guaranteed on-resistance at the lowest BIAS switchover voltage.

To reduce switching noise for smaller MOSFETs, use a series resistor in the BST path and additional gate capacitance. Contact factory for guidance using gate resistors.

Current-Sense Measurement

For best current-sense accuracy and overcurrent protection, use a ±1% tolerance current-sense resistor between the inductor and output, as shown in Figure 2 (A). This configuration continuously monitors inductor current, allowing accurate current-limit protection. Use low-inductance current-sense resistors for accurate measurement.

Alternatively, high-power applications can reduce the overall power dissipation by connecting a DCR sensing network across the inductor Figure 2 (B). Select DCR network based on the following equations:

R_{CSHL} = (\frac{R_{2}}{R_{1} + R_{2}}) R_{DCR} and R_{DCR} = \frac{L}{C_{eq}} (\frac{1}{R_{1}} + \frac{1}{R_{2}})

where R_CSHL is the required current-sense resistor based on the current-limit threshold (V_LIMIT) and R_DCR is the inductor DC resistance. If DCR sense is the preferred current-sense method, select R1 ≤ 1kΩ. See Figure 2 (B).

Carefully observe the Layout Recommendations to ensure the noise and DC errors do not corrupt the differential current-sense signals seen by CS and OUT. Place the sense resistor close to the controller CS/OUT pins with short, direct traces, making a Kelvin-sense connection to the current-sense resistor.

Input Capacitor in Buck Converter

Select input capacitor to satisfy the following conditions

Withstand input ripple current in buck power stage
Limit the input voltage ripple

The RMS current in the input capacitor is given by:

I_{CIN . RMS} = I_{LOAD (MAX)} \sqrt{D \times (1 - D)}

The input voltage ripple is composed of ΔV_IN.C (caused by the capacitor discharge) and ΔV_IN._ESR (caused by the ESR of the input capacitor) given by:

{ΔV}_{IN . C} = \frac{I_{LOAD (MAX)} x D (1 - D)}{C_{IN} x f_{SW}} and {ΔV}_{IN . ESR} = {ESR}_{CIN} (I_{LOAD (MAX)} + \frac{{ΔI}_{L}}{2})

I_LOAD(MAX) is the maximum output current, ΔI_L is the peak-to-peak inductor current ripple, and C_IN is the input capacitor.

The internal 5V linear regulator (BIAS) includes an output UVLO with hysteresis to avoid unintentional chattering during turn-on. Use additional bulk capacitance if the input source impedance is high. At lower input voltages, additional input capacitance helps avoid possible undershoot below the undervoltage lockout threshold during transient loading.

Output Capacitor in Buck Converter

The output capacitor is selected to meet ripple requirements, both in steady state and during transients. Low ESR ceramic capacitors can be utilized.

The steady state output ripple has capacitive and ESR based components given by:

{ΔV}_{OUT . C} = \frac{1}{8} \frac{{ΔI}_{L}}{f_{sw} C_{OUT}} and {ΔV}_{OUT . ESR} = {ΔI}_{L} \times {ESR}_{COUT}

When using low-capacity filter capacitors, such as ceramic capacitors, capacitor selection is usually driven by the need to limit undershoot and overshoot during load transients. The design should be verified in the lab to ensure undershoot and overshoot requirements are met.

Control Loop / Compensation

The IC uses a peak current-mode control scheme that regulates the output voltage by controlling the required current through the external inductor. Current mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor, resulting in a smaller phase shift and requiring less elaborate error-amplifier compensation than voltage-mode control.

A single series resistor (R_C) and capacitor (C_C) is required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering (see Figure 3). For high-ESR (non-ceramic) output capacitors, the zero created by the capacitance and ESR can be close to or lower than the desired closed-loop crossover frequency. To stabilize a high-ESR (non ceramic) output capacitor loop, add another compensation capacitor (C_F) from COMP to AGND to cancel this ESR zero.

The basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier as shown in Figure 3. The DC gain of the modulator is given by:

${GAIN}_{MOD (DC)} = g_{mc} x R_{LOAD}$

where R_LOAD = V_OUT/I_LOAD(MAX) in Ω and g_mc = 1/(A_VCS x R_CS) in S. A_VCS is the voltage gain of the current-sense amplifier and is typically 13V/V. R_CS is current-sense resistor in Ω. When using DCR sensing network, replace R_CS with R_CSHL.

In a current-mode step-down converter, the output capacitor and the load resistance introduce a pole at the frequency:

f_{pMOD} = \frac{1}{2 π x C_{OUT} x R_{LOAD}}

The output capacitor and its ESR also introduce a zero given by:

$f_{zMOD} = \frac{1}{2 π x {ESR}_{COUT} x C_{OUT}}$

When C_OUT is composed of “n” identical capacitors in parallel, the resulting C_OUT = n x C_OUT(EACH), and ESR_COUT = ESR_COUT(EACH)/n. Note that the capacitor zero for a parallel combination of alike capacitors is the same as for an individual capacitor.

The feedback voltage-divider has a gain of GAIN_FB = V_FB/V_OUT, where V_FB is 0.7V (typ).

The transconductance error amplifier has a DC gain of GAIN_EA(DC₎ = g_m,EA x R_OUT,EA, where g_m,EA is the error amplifier transconductance, which is 450µS (typ), and R_OUT,EA is the output resistance of the error amplifier, which is 30MΩ (typ).

A dominant pole (f_dpEA) is set by the compensation capacitor (C_C) and the amplifier output resistance (R_OUT,EA). A zero (f_zEA) is set by the compensation resistor (R_C) and the compensation capacitor (C_C). There is an optional pole (f_pEA) set by the compensation capacitor to cancel the output capacitor ESR zero if it occurs near the crossover frequency (f_C, where the loop gain equals 1 (0dB)).

f_{dpEA} = \frac{1}{2 π x C_{C} x (R_{OUT, EA} + R_{C})} f_{zEA} = \frac{1}{2 π x C_{C} x R_{C}} f_{pEA} = \frac{1}{2 π x C_{F} x R_{C}}

The loop-gain crossover frequency (f_C) should be set below 1/5th of the switching frequency and much higher than the power-modulator pole (f_pMOD). Select a value for f_C in the range shown below:

f_{pMOD} ≪ f_{C} \leq \frac{f_{SW}}{5}

At the crossover frequency, the total loop gain is unity. Select R_C based on the target crossover frequency:

R_{C} = f_{C} \times \frac{V_{OUT}}{V_{FB}} \times \frac{2 π}{g_{m, EA}} \times A_{VCS} R_{CS} \times C_{OUT}

Set the error-amplifier compensation zero formed by R_C and C_C at f_pMOD:

C_{C} = \frac{1}{2 π \times f_{pMOD} \times R_{C}}

If f_zMOD is less than 5 x f_C, add a second capacitor C_F from COMP to AGND using the equation below:

C_{F} = \frac{1}{2 π \times f_{zMOD} \times R_{C}}

As the load current decreases, the modulator pole frequency also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same.

Layout Recommendations

PCB layout is critical for stable operation, low noise, and high efficiency. Use the checklist below to achieve good circuit performance (See Figure 4 for an example):

Place the input capacitor (C_IN), the high-side MOSFET (QH), and the low-side MOSFET (QL) so that the "input loop" area involving high di/dt is minimized.
Use low-ESR/ESL ceramic capacitors (C_IN) close to the input loop. Bulk capacitor can be further away.
Place the output capacitors (C_OUT) so that input and output capacitor grounds are close together. In addition, connect this common ground connection to ground plane layer(s) using multiple vias.
Use short and wide traces/areas for high current paths (V_IN, V_OUT, LX, PGND). If possible, run them on multiple layers in parallel to minimize resistance.
Minimize the area of high dv/dt nodes (LX) to the extent permitted by heating considerations.
Route gate drive forward and return paths together using short and wide traces to minimize loop impedance. Wherever possible, use traces wider than 25 mils for outer layers and 50 mils for inner layers.
High-side gate charging path includes C_BST. Place C_BST as close to the IC pins (BST/LX) as possible.
Low-side gate charging path includes C_BIAS. Place C_BIAS as close to the IC pins (BIAS/PGND) as possible.
Low-side gate charge/discharge path includes PGND. Ensure that a continuous PGND plane is present under DL path.
Place the sense resistor (R_CS) close to the CS/OUT pins. Use Kelvin connections across the sense resistor (R_CS) and route differentially to the IC pins (CS/OUT). Make the sense traces as short as possible. Place a 22nF capacitor near the CS/OUT pins to minimize noise due to sense trace inductance.
Use AGND as the reference ground for sensitive analog signals (FB, COMP). Connect the ground side of the bottom feedback resistor (R_FB1) and compensation components (C_C, C_F) to AGND.
Route sensitive traces (FB, CS/OUT) away from noisy (high dv/dt and di/dt) areas (BST, LX, DH, DL).
Connect AGND/PGND under the IC at one point (Figure 4).
Connect IC exposed pad through multiple vias to ground plane layer(s).
Use thicker copper (preferably 2oz/ft²) for higher current designs for better efficiency and thermal performance.