| POWER |
| 7 | 9 | 13 | VDDF | Output of the DC-DC Converter. Bypass to GNDF with 1μF||0.01μF capacitors. The 0.01μF capacitor should be placed as close as possible to the pin. | |
| 8 | 10 | 1, 14 | GNDF | Field-Side Ground for Everything Except the ADC Front-End and Voltage Reference | VDDF |
| 11 | 13 | 17 | VDDL | Power Input for the Logic-Side. Bypass with 1μF||0.01μF capacitors to GNDL. | |
| 10 | 12 | 16 | VDDPL | Power Input for the Isolated DC-DC Converter. The DC-DC converter powers the field-side. Bypass with 1μF||0.01μF capacitors to GNDL. | VDDL |
| 9 | 11 | 15, 28 | GNDL | Power and Signal Ground for All Logic-Side Pins | |
| – | – | 2, 27 | N.C. | Not Connected | |
| ANALOG |
| 1 | 1 | 3 | REF | External Filter Capacitor. Connect a 1μF||0.01μF capacitor from REF to AGND. | VDDF |
| 2 | 2 | 4 | AGND | Analog Ground Reference for AIN_ and REF | VDDF |
| 3 | 3 | 5 | AIN1 | Analog Input Channel 1 The ADC measures the voltage on this pin with respect to AGND | VDDF |
| 4 | 4 | 7 | AIN2 | Analog Input Channel 2. The ADC measures the voltage on this pin with respect to AGND. | VDDF |
| 5 | 6 | 9 | AIN3 | Analog Input Channel 3. The ADC measures the voltage on this pin with respect to AGND. | VDDF |
| 6 | 7 | 11 | AIN4 | Analog Input Channel 4. The ADC measures the voltage on this pin with respect to AGND. | VDDF |
| - | 5, 8 | 6, 8, 10, 12 | AGND | Analog Ground Reference for AIN_ and REF | VDDF |
| DIGITAL |
| 12 | 16 | 22 | SDO | Serial Data Out for SPI Interface (MISO) | VDDL |
| 13 | 17 | 23 | SDI | Serial Data Input for SPI Interface (MOSI) | VDDL |
| 14 | 18 | 24 | SCLK | Serial Clock for SPI Interface | VDDL |
| 15 | 19 | 25 | CS | Chip Select for SPI Interface. Assert low to enable SPI functions and SDO. SDO and COUT_ are high impedance when CS is high. | VDDL |
| - | 14 | 18 | COUT1 | Digital Comparator Output. COUT1 is high when AIN1 is above the upper threshold (COUTHI1) and low when AIN1 is below the lower threshold (COUTLO1) in digital input mode. See the Digital Status Mode section. | VDDL |
| - | 15 | 19 | COUT2 | Digital Comparator Output. COUT2 is high when AIN2 is above the upper threshold (COUTHI2) and low when AIN2 is below the lower threshold (COUTLO2) in digital input mode. See the Digital Status Mode section. | VDDL |
| - | - | 20 | COUT3 | Digital Comparator Output. COUT3 is high when AIN3 is above the upper threshold (COUTHI3) and low when AIN3 is below the lower threshold (COUTLO3) in digital input mode. See the Digital Status Mode section. | VDDL |
| - | - | 21 | COUT4 | Digital Comparator Output. COUT4 is high when AIN4 is above the upper threshold (COUTHI4) and low when AIN4 is below the lower threshold (COUTLO4) in digital input mode. See the Digital Status Mode section. | VDDL |
| 16 | 20 | 26 | INT | Open-Drain Output that Asserts Low during a number of Different Error Conditions. The cause of the error is latched in the INTERRUPT STATUS register. See the Diagnostic and Fault Reporting Features section for details on clearing INT. | VDDL |
