Electrical Characteristics

Electrical Characteristics
(V_DDL - V_GNDL = 1.71V to 5.5V, V_DDPL - V_GNDL = 3.0V to 5.5V, C_DDF = 1μF, C_REF = 1μF. Limits are 100% tested at T_A=+25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) (Note 1 Note 2))
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
LOGIC-SIDE POWER SUPPLY
Logic Power Supply	V_DDL		1.71		5.5	V
Logic Supply Current	I_DDL			1	2.5	mA
Logic-Supply UVLO Threshold	V_{DDL_UVLO}		1.5	1.6	1.66	V
Logic-Supply UVLO Hysteresis	V_{DDL_UHYS}			50		mV
Logic Power-Up Time	t_LPU	Valid SPI access		0.6	1	ms
Isolated DC-DC Supply	V_DDPL		3.0	3.3	5.5	V
Isolated DC-DC Supply Current	I_DDPL	V_DDPL = 3.3V		7	10	mA
Isolated DC-DC Supply UVLO Threshold	V_{DDPL_UVLO}		2.7	2.8	2.95	V
Isolated DC-DC Supply UVLO Hysteresis	V_{DDPL_UHYS}			100		mV
FIELD-SIDE PARAMETERS
V_DDF Supply Voltage	V_DDF	Internally generated	2.7	3.1	5.5	V
Isolated DC-DC Power Up Time	t_PWRUP	C_DDF = 1 µF			10	ms
ADC AND COMPARATOR
Input-Voltage Range	V_AIN		0		1.8	V
ADC Resolution			12			Bits
Gain Error	GE	V_AIN = 98% V_REF, excluding offset error and reference error	-0.2		+0.2	%FS
Offset Error	OE	V_AIN = 2% V_REF, offset calculated	-0.1		+0.1	%FS
Differential Nonlinearity	DNL				±1.5	LSB
Integral Nonlinearity	INL	Included in the gain and offset window			±2.0	LSB
Input-Leakage Current	IN_LKG		-600		+600	nA
Throughput per Channel			18	20	22	ksps
Latency (No filtering)		AIN# step input to COUT transition (Note 3)		75		µs
Latency (4 Readings)		AIN# step input to COUT transition (Note 3)		300		µs
CMTI		(Note 4)		50		kV/µs
INTERNALVOLTAGE REFERENCE
Nominal Output Voltage	V_REF	T_A = +25°C	1.78	1.80	1.82	V
Output-Voltage Accuracy	V_{REF_TOL}	T_A = -25°C to +85°C	-1.5		+1.5	%
Output-Voltage Accuracy	V_{REF_TOL}	T_A= -40°C to +125°C	-2		+2	%
Output-Voltage Temperature Drift	T_CVOUT			50		ppm/°C
LOGIC INTERFACE (SCLK, SDI, SDO, CS, COUT, INT)
Input Logic-High Voltage	V_IH	SCLK, SDI, CS	0.7 x V_DDL			V
Input Logic-Low Voltage	V_IL	SCLK, SDI, CS			0.3 x V_DDL	V
Input Hysteresis	V_HYST	SCLK, SDI, CS		50		mV
Input Leakage Current	I_{IN_LKG}	SCLK, SDI, CS	-1		+1	µA
Input Capacitance	C_IN	SCLK, SDI, CS, f = 1MHz		2		pF
Output Logic-High Voltage	V_OH	SDO, COUT, sourcing 4mA	V_DDL-0.4			V
Output Logic-Low Voltage	V_OL	SDO, COUT, INT, sinking 4mA			0.4	V
Output High-Impedance Leakage Current	I_OLKG	INT, SDO	-1		+1	µA
SPI TIMING CHARACTERISTICS
SCLK Clock Frequency	f_SCLK				10	MHz
SCLK Clock Period	t_SCLK		100			ns
SCLK Pulse-Width High	t_SCLKH		40			ns
SCLK Pulse-Width Low	t_SCLKL		40			ns
CS Fall-to-SCLK Rise Time	t_CS(LEAD)		20			ns
SCLK Fall-to-CS Rise Time	t_CS(LAQ)		80			ns
SDI Hold Time	t_DINH		20			ns
SDI Setup Time	t_DINSU		20			ns
SDO Disable Time (CS Rising to SDO Three- State)	t_DOUT_(DIS)		40			ns
Output Data Propagation Delay	t_DO				50	ns
Inter-Access Gap	t_IAG		920			ns

Note 1:	All devices are 100% production tested at T_A = +25C. Specifications for all temperature limits are guaranteed by design.
Note 2:	All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to their respective ground (GNDL or GNDF), unless otherwise noted.
Note 3:	Latency numbers are based on the following condition: a full-scale step is applied at the ADC input and COUTHI_ (register address 0x9 to 0xC) upper threshold (THU) is set to maximum value (0xFFFh). Latency is the delay from the step at the ADC input to the digital comparator output.
Note 4:	CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to both rising and falling common-mode voltage edges. Tested with the transient generator connected between GNDF and GNDL (V_CM = 1000V).

Timing Diagram

Insulation Characteristics16-pin Wide SOIC

PARAMETER	SYMBOL	CONDITIONS	VALUE	UNITS
Partial Discharge Test Voltage	V_PR	Method B1 = V_IORM x 1.875 (t = 1s, partial discharge < 5pC)	2250	V_P
Maximum Repetitive-Peak-Isolation Voltage	V_IORM	(Note 5)	1200	V_P
Maximum Working-Isolation Voltage	V_IOWM	Continuous RMS voltage (Note 5)	848	V_RMS
Maximum Transient-Isolation Voltage	V_IOTM	(Note 5)	7000	V_P
Maximum Withstanding-Isolation Voltage	V_ISO	f_SW = 60Hz, duration = 60s (Note 5, Note 6)	5000	V_RMS
Maximum Surge-Isolation Voltage	V_IOSM	Basic Insulation, 1.2/50μs pulse per IEC61000-4-5	10000	V_P
Insulation Resistance	R_IO	V_IO= 500V, T_A = 25°C	> 10¹²	Ω
		V_IO= 500V, 100°C ≤ T_A ≤ 125°C	> 10¹¹
		V_IO= 500V, T_S = 150°C	> 10⁹
Barrier Capacitance Field Side-to-Logic Side	C_IO	f_SW = 1MHz (Note 7)	2	pF
Minimum Creepage Distance	CPG		8	mm
Minimum Clearance Distance	CLR		8	mm
Internal Clearance		Distance through insulation	0.015	mm
Comparative Tracking Index	CTI	Material Group II (IEC 60112)	> 400
Climate Category			40/125/21
Pollution Degree (DIN VDE 0110, Table 1)			2

20-pin and 28-pin SSOP

PARAMETER	SYMBOL	CONDITIONS	VALUE	UNITS
Partial Discharge Test Voltage	V_PR	Method B1 = V_IORM x 1.875 (t = 1s, partial discharge < 5pC)	1182	V_P
Maximum Repetitive-Peak-Isolation Voltage	V_IORM	(Note 5)	630	V_P
Maximum Working-Isolation Voltage	V_IOWM	Continuous RMS voltage (Note 5)	445	V_RMS
Maximum Transient-Isolation Voltage	V_IOTM	(Note 5)	5300	V_P
Maximum Withstanding-Isolation Voltage	V_ISO	f_SW = 60Hz, duration = 60s (Note 5, Note 6)	3750	V_RMS
Maximum Surge-Isolation Voltage	V_IOSM	Basic Insulation, 1.2/50μs pulse per IEC61000-4-5	10000	V_P
Insulation Resistance	R_IO	V_IO= 500V, T_A = 25°C	> 10¹²	Ω
		V_IO= 500V, 100°C ≤ T_A ≤ 125°C	> 10¹¹
		V_IO= 500V, T_S = 150°C	> 10⁹
Barrier Capacitance Field Side-to-Logic Side	C_IO	f_SW = 1MHz (Note 7)	2	pF
Minimum Creepage Distance	CPG		5.5	mm
Minimum Clearance Distance	CLR		5.5	mm
Internal Clearance		Distance through insulation	0.015	mm
Comparative Tracking Index	CTI	Material Group II (IEC 60112)	> 400
Climate Category			40/125/21
Pollution Degree (DIN VDE 0110, Table 1)			2

Note 5:	V_ISO, V_IOWM, and V_IORM are defined by the IEC 60747-5-5 standard.
Note 6:	Product is qualified at V_ISO for 60s and 100% production tested at 120% of V_ISO for 1s.
Note 7:	Capacitance is measured with all pins on field-side and logic-side tied together.

ESD and Transient Immunity Characteristics

PARAMETER	SYMBOL	CONDITIONS	VALUE (TYP)	UNITS
Surge	AIN_ to GNDF	≥ 60kΩ input resistor, IEC 61000-4-5 1.2µs/50µs pulse	±7.2	kV
Surge	AIN_ to AIN_	≥ 60kΩ input resistors, IEC 61000-4-5 1.2µs/50µs pulse	±4	kV
EFT	AIN_ to GNDF	Capacitive clamp to input cable pair (AIN_- GNDF) with 60kΩ input divider resistor connected AIN_- GNDF, 1nF Y-CAP to earth, IEC61000-4-4	±4	kV
ESD	AIN_ Contact	≥ 60kΩ resistor in series with AIN_ with respect to GNDF, IEC 61000-4-2	±8	kV
	AIN_ Air Gap	≥ 60kΩ resistor in series with AIN_ with respect to GNDF, IEC 61000-4-2	±15
	Any pin to Any pin	Human Body Model	±3

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