Detailed Description

The MAX22530–MAX22532 family consists up of 12-bit, 4-channel ADCs with either a 3.5kV_RMS or 5kV_RMS isolated SPI interface depending upon the package option. Additional features include comparators with programmable upper and lower threshold levels. The ADC and all field-side circuits are powered by an integrated, isolated, DC-DC converter that allows field-side functionality to be verified even when there is no input signal or other field-side supply. This makes the MAX22530–MAX22532 family ideally suited for high-density, multirange, group-isolated, binary-input modules, and provides a complete solution to any system that requires monitoring inputs without a separate isolated power supply. 

The devices’ ADC employs a 12-bit SAR architecture with a nominal sampling rate of 20ksps per channel and has an input-voltage range of 0V to +1.8V with respect to AGND. After power-up, the ADC runs continually at the nominal sampling rate. The 12-bit unfiltered ADC reading and filtered ADC reading are both available through the SPI interface. Filtering averages the most recent 4 readings. For rapid response without requiring the SPI interface, the MAX22530–MAX22532 family provides the output of a digital comparator (COUT_) that compares user-programmed thresholds to the ADC reading or the filtered ADC reading. The comparator has two thresholds, the comparator output is high when the input voltage is above the upper threshold and low when it is below the lower threshold in default digital-input mode. The response time of the comparator is less than 75μs (typ) with filtering disabled. With filtering enabled, the comparator uses the moving average of the last 4 ADC readings for a response time of 300μs (typ). The comparator output pin (COUT_) changes based on the latest ADC reading, the upper threshold (COTHI_[11:0], register address 0x9, 0xA, 0xB and 0xC) and the lower threshold (COTLO_[11:0], register address 0x10, 0xD, 0xE and 0xF) according to the CO_MODE_ setting. If enabled, the interrupt pin INT asserts whenever COUT_ changes.

The MAX22530-MAX22532 family features a precision internal voltage reference. The 1.8V internal reference has a maximum error of ±2% over the entire operating temperature range. The MAX22530-MAX22532 family is not intended to be used with an external voltage reference.

The input signal can be recognized in two different ways; one is the digital input mode and the other is the digital status mode. The mode of operation is set for each input channel in the COUTHI_ registers (address 0x9, 0xA, 0xB and 0xC) with the CO_MODE bits.

The Digital input mode (see Figure 3) treats the digitized input (from the ADC) as a digital signal of “1” or “0” with hysteresis where the values for “1” and “0” are set by the upper- and lower-limit thresholds programmed into registers COUTHI_ and COUTLO_ (see COUT_BLK in register map).

The Digital status mode (see Figure 4) monitors the input in “Normal” status vs. “OVLO/UVLO” status:

A simplified view of the isolated power and data transfer sections is shown in the Functional Diagram. The logic-side supply V_DDPL powers an integrated, inductively coupled DC-DC converter that generates a nominal field supply V_DDF of 3.1V with just enough output current to power the field-side of the MAX22530–MAX22532 family. Note that V_DDF is not intended to power an external load.

Serial data is transferred by capacitively-isolated differential transceivers. To verify reliable communication through the isolation barrier, a cyclic redundancy check (8-bit CRC) is embedded in the transmitted serial data streams. If a CRC fails, the data is discarded, and no action is taken. If CRC fails, the SPICRC bits in the INTERRUPT STATUS register is set and INT is asserted if the ENCRC interrupt enable bit is set in the INTERRUPT ENABLE register.

An SPI interface is used for transferring configuration, control, and diagnostic data as well as ADC readings between a host (FPGA or microcontroller) and the MAX22530–MAX22532. The interface consists of four signals: SCLK, CS, SDI and SDO, and does not support daisy-chain configuration. An optional CRC improves reliability in the data communication to and from the MAX22530–MAX22532. This feature, disabled by default after reset or power-up, can be enabled or disabled at any time through the SPI interface. When enabled, it affects both read and write SPI transactions.

SPI communication includes the following features (see Table 3):

The functionality of each SPI pin can be summarized as follows:

The MAX22530–MAX22532 offers burst and single-register SPI transactions. Single-register SPI transactions can be used to access any register address and are 3-bytes long without CRC and 4-bytes long with CRC. The CRC byte is calculated on the previous 3 bytes. The single-register SPI transaction format consists of a 6-bit register address, a read/write bit, a burst mode bit, 16 bits of payload, and the optional CRC byte, as illustrated in Table 1 for write transaction and in Table 2 for read transactions. See Figure 1 and Figure 2 for SPI write and read timing diagrams.

Note: The BURST bit in the header is ignored in SPI write transactions

Burst mode can only be used for reading the filtered or unfiltered ADC data registers and the interrupt status register in one SPI transaction. Burst SPI transactions are 11-bytes long without CRC and 12-bytes long with CRC. The CRC byte is calculated on the previous 11 bytes. The burst SPI transaction format consists of the 6-bit register address for ADC1 or FADC1, a read/write bit, a burst mode bit, the contents of the four filtered or unfiltered ADC registers depending on the 6-bit address entered, the content of the interrupt status register, and the optional CRC byte, as illustrated in Table 3. The burst bit is ignored for all other register addresses during read transactions.

The MAX22530–MAX22532 knows that it should receive 24, 32, 88, or 94 bits depending on the combination of CRC setting and burst mode. If more SPI cycles than expected are received, the transaction is executed. If fewer SPI cycles than expected are received, the transaction fails.

The MAX22530–MAX22532 continuously monitor multiple possible fault conditions, and a hardware alert is provided through the open drain INT pin, which asserts low when an enabled fault is detected. The possible faults are: ADC functionality error, SPI framing error, CRC errors from SPI communications, and loss of internal isolated data stream.

The bits in the INTERRUPT ENABLE (0x13) register determine how the INT output responds to the various error conditions and asserts the INT output if the corresponding bit is enabled in the INTERRUPT ENABLE register.

If the corresponding bit in the INTERRUPT ENABLE register is not set, when an error is flagged, INT is not asserted, but the bit in the INTERRUPT STATUS register (0x12) is still latched and remains set until the register is read, which automatically clears all bits in the INTERRUPT STATUS register. Note that if a fault condition still exists when the register is read, the cleared fault bit is immediately set again.

In a typical application, INT triggers an interrupt routine in the microcontroller or FPGA, which reads the INTERRUPT STATUS register to determine the cause of the interrupt.

ADC functionality is checked by looking for changes in the ADC output. To ensure that a change should have occurred, a special test measurement is made while injecting a small current at the input of the ADC. This special measurement used for ADC functionality verification is interleaved between normal measurements and does not affect the ADC sampling time. If the ADC reading does not change, or data is outside of the limits for at least four frames, an ADC functional failure is declared and bit FADC (bit 11) in the INTERRUPT STATUS (0x12) register is set.

After CS transitions from low to high, if the number of bits clocked in while CS was low is not 24, 32, 88, or 96 bits, an SPI framing error is declared and bit SPIFRM (bit 9) in the INTERRUPT STATUS (0x12) register is set. The instruction in the SPI shift register is not decoded and no register value is changed.

The field-side sends ADC data across the isolation barrier to the logic-side every 50μs except for the startup period. Field-side loss-of-data (FLD) interrupts are masked for the first 100ms of operation after power-on or reset, and after that if an internal monitoring signal is not received, an error is flagged. If the periodic field-side data is not received, a loss-of-data-stream fault is declared and bit FLD (bit 10) in the INTERRUPT STATUS (0x12) register is set. It is possible to recover from a loss of data stream fault by asserting a hard reset using bit REST (bit 0) in the CONTROL (0x14) register, which causes field-side power to be rebooted and returns all of the registers to their default state, requiring the MAX22530–MAX22532 to go through the startup configuration process.

Internal communication across the isolation barrier includes a CRC code to ensure that corrupt data does not cause system problems. If the CRC indicates an error, the received data is discarded. If six consecutive CRCs fail, a CRC fault is declared and bit SPICRC (bit 8) in the INTERRUPT STATUS (0x12) register is set.

The CONTROL (0x14) register includes a number of bits which the host can program and which take immediate effect on the device.

If the control bit REST is set to 1, the field-side power supply is shut down and restarted, and the main reset input to the digital core is asserted, resulting in setting the digital core back to its power-on reset state and all registers are brought back to their default values, including the control bit, REST.

The software reset is initiated by setting bit SRES to 1. Unlike the hardware reset that is effective immediately after assertion, SRES takes affect after the completion of the frame, during which it is asserted. At that time, the digital core is reset and all registers are brought back to their default values. The field-side power supply is not affected by SRES.

The CLRPOR bit can be set to 1 to clear the ‘Wake Up from Power-On Reset’ POR bit in the PROD_ID (0x00) register. Note that a hardware reset (REST) causes the POR bit to be reasserted, but a software reset, SRES, has no effect on the status bit POR.

Setting bit DISPWR to 1 disables field-side power (V_DDF), effectively stopping ADC conversions. The logic-side or digital core is not affected.

The control bits FLT_CLR_1 to FLT_CLR_4 can be set to 1 to clear the ADC moving average filter for that specific channel at the start of the frame following this assertion. Once the filter reset operation takes place the control bits remain set at 0 for normal operation.

The control bit ECOM can be set to 1 to apply the settings of COUTHI1 and COUTLO1 to all four channels regardless of what values are programmed in the high and low threshold registers for the other three channels. Setting the ECOM bit to 1 does not change what the host reads back from the threshold registers for channels 2 to 4.

If control bit ENCRC is 0, CRC functionality is not enabled, and SPI transactions are 24-bits in length. But if control bit ENCRC is 1, CRC functionality is enabled making each SPI transaction 32-bits in length. At power-on, or after a hardware or software reset, the default CRC is disabled. All SPI transactions following the write transaction that sets ENCRC must have the 8-bit CRC suffix.

In a system, the MAX22530–MAX22531 device operations can be monitored by the host (typically a microcontroller or FPGA) by either polling the ADC_ registers or by using the end-of-conversion (EOC) interrupt bit in the INTERRUPT ENABLE (0x13) register to assert the interrupt pin, INT. The ADC core continually digitizes the inputs for the four channels in succession, and the host can determine the ADC conversion state by polling the ADCs bit in each ADC_ register (bit 15), or by enabling the EOC to be shown on the INT every 50 µs. If the EOC interrupt is enabled, bit EOC (bit 12) in the INTERRUPT STATUS (0x12) register is set to 1 and causes the INT pin to be asserted for a duration of 10µs at the end of channel 4 ADC (ADC_4) conversion. After 10µs the INT pin is deasserted whether the INTERRUPT STATUS register is read or not.

At that time, the unfiltered (ADC_) and filtered (FADC_) data are available to be read through SPI, as well as the comparator status and comparator-related interrupts.

If the host is polling the SPI interface for ADC status, the burst read command allows it to read all four ADC registers (ADC1 to ADC4, or FADC1 to FADC4. See ADC_STATUS BLK in register map section) in addition to the INTERRUPT STATUS register. Bit 15 in each ADC_ register is the ADCs bit. If ADCs is 0 the register contents have been updated (new conversion data) since the last read operation. By performing a data read operation, the ADCs bit is automatically set to 1, indicating the data has not been refreshed since the last read operation. Upon receiving the INT signal, the host interrupt service routine can perform a burst read, which automatically clears the bits in the INTERRUPT STATUS register, thereby deasserting the INT pin.

If the host does not access the ADC_ data registers at least once per frame (whether by polling or responding to INT being asserted) then data loss occurs, and the register contents are overwritten with new conversion data.

If the ADC_ data register refreshing event occurs while CS is low (i.e., during an SPI transaction), the data refreshing event is postponed until the deassertion of CS. This scheme eliminates possible data corruption and data loss. However, it assumes that the rate of the SPI transaction is equal to or greater than the rate of ADC sampling (20ksps), and that the duration of any SPI transaction is shorter than that of a 4-channel conversion frame. The host can safely read the ADC_ data registers during the 50µs following the assertion of the end-of-conversion interrupt.

The host can set the limits against which the ADC data is compared. The host can select if a given channel uses the unfiltered (ADC_) or the filtered ADC (FADC_) data for comparison against the limits using the control bits CO_MODE (bit 15) and CO_IN_SEL (bit 14) in each COUTHI_ register. The CO_MODE bits determine the comparator mode of operation (Digital Data Mode if the bit is set to 0 or Digital Status Mode if the bit is set to 1) and CO_IN_SEL selects between unfiltered ADC data (bit set to 0) of filtered ADC data (bit set to 1). The status of the comparison for each channel can be read from register COUT STATUS (0x11).

In addition to the diagnostics bits, the comparator outputs can be programmed to assert the INT pin if enabled. If a positive edge is detected by the comparator, the bit CO_POS_ is set to 1 indicating the ADC_ data is greater than the upper limit (COUTHI_). Similarly, if a negative edge is detected by the comparator, the bit CO_NEG_ is set to 1 indicating the ADC_ data is lower than the lower limit (COUTLO_).

Changes to comparator control register contents take effect on the next frame. For example, if COUTHI_4[11:0] is changed during frame N, the new threshold value is used starting frame N+1.

To clear an interrupt and deactivate the INT pin, the host must perform a read operation of the INTERRUPT STATUS register. All bits in the INTERRUPT STATUS register are “Read Clears All.” Interrupts are cleared whether the CRC is properly decoded by the host or not. Note that if a fault condition still exists when the register is read, the cleared fault bit is immediately set again.

If an interrupt is not set at the time that the INTERRUPT STATUS register is read, and if that interrupt gets asserted while the interrupt register is being read, that interrupt bit is not cleared upon the end of the SPI read transaction.

However, if an interrupt that is set at the time that the interrupt register is read, and if another identical interrupt gets asserted while the interrupt register is being read, that interrupt bit is cleared upon the end of the SPI transaction. This means that the host should read the interrupt register upon assertion of INT, or poll the interrupt registers several times per conversion cycles to avoid missing interrupts.

In a system, the MAX22530–MAX22531 device operations can be monitored by the host (typically a microcontroller or FPGA) by either polling the ADC_ registers or by using the end-of-conversion (EOC) interrupt bit in the INTERRUPT ENABLE (0x13) register to assert the interrupt pin, INT. The ADC core continually digitizes the inputs for the four channels in succession, and the host can determine the ADC conversion state by polling the ADCs bit in each ADC_ register (bit 15), or by enabling the EOC to be shown on the INT every 50 µs. If the EOC interrupt is enabled, bit EOC (bit 12) in the INTERRUPT STATUS (0x12) register is set to 1 and causes the INT pin to be asserted for a duration of 10µs at the end of channel 4 ADC (ADC_4) conversion. After 10µs the INT pin is deasserted whether the INTERRUPT STATUS register is read or not.

At that time, the unfiltered (ADC_) and filtered (FADC_) data are available to be read through SPI, as well as the comparator status and comparator-related interrupts.

If the host is polling the SPI interface for ADC status, the burst read command allows it to read all four ADC registers (ADC1 to ADC4, or FADC1 to FADC4) in addition to the INTERRUPT STATUS register. Bit 15 in each ADC_ register is the ADCs bit. If ADCs is 0 the register contents have been updated (new conversion data) since the last read operation. By performing a data read operation, the ADCs bit is automatically set to 1, indicating the data has not been refreshed since the last read operation. Upon receiving the INT signal, the host interrupt service routine can perform a burst read, which automatically clears the bits in the INTERRUPT STATUS register, thereby deasserting the INT pin.

If the host does not access the ADC_ data registers at least once per frame (whether by polling or responding to INT being asserted) then data loss occurs, and the register contents are overwritten with new conversion data.

If the ADC_ data register refreshing event occurs while CS is low (i.e., during an SPI transaction), the data refreshing event is postponed until the deassertion of CS. This scheme eliminates possible data corruption and data loss. However, it assumes that the rate of the SPI transaction is equal to or greater than the rate of ADC sampling (20ksps), and that the duration of any SPI transaction is shorter than that of a 4-channel conversion frame. The host can safely read the ADC_ data registers during the 50µs following the assertion of the end-of-conversion interrupt.

The host can set the limits against which the ADC data is compared. The host can select if a given channel uses the unfiltered (ADC_) or the filtered ADC (FADC_) data for comparison against the limits using the control bits CO_MODE (bit 15) and CO_IN_SEL (bit 14) in each COUTHI_ register. The CO_MODE bits determine the comparator mode of operation (Digital Data Mode if the bit is set to 0 or Digital Status Mode if the bit is set to 1) and CO_IN_SEL selects between unfiltered ADC data (bit set to 0) of filtered ADC data (bit set to 1). The status of the comparison for each channel can be read from register COUT STATUS.

In addition to the diagnostics bits, the comparator outputs can be programmed to assert the INT pin if enabled. If a positive edge is detected by the comparator, the bit CO_POS_ is set to 1 indicating the ADC_ data is greater than the upper limit (COUTHI_). Similarly, if a negative edge is detected by the comparator, the bit CO_NEG_ is set to 1 indicating the ADC_ data is lower than the lower limit (COUTLO_).

Changes to comparator control register contents take effect on the next frame. For example, if COUTHI_4[11:0] is changed during frame N, the new threshold value is used starting frame N+1.

To clear an interrupt and deactivate the INT pin, the host must perform a read operation of the INTERRUPT STATUS register (0x12). All bits in the INTERRUPT STATUS register are “Read Clears All.” Interrupts are cleared whether the CRC is properly decoded by the host or not. Note that if a fault condition still exists when the register is read, the cleared fault bit is immediately set again.

If an interrupt is not set at the time that the INTERRUPT STATUS register is read, and if that interrupt gets asserted while the interrupt register is being read, that interrupt bit is not cleared upon the end of the SPI read transaction.

However, if an interrupt that is set at the time that the interrupt register is read, and if another identical interrupt gets asserted while the interrupt register is being read, that interrupt bit is cleared upon the end of the SPI transaction. This means that the host should read the interrupt register upon assertion of INT, or poll the interrupt registers several times per conversion cycles to avoid missing interrupts.

The MAX22530-MAX22532 provide basic galvanic isolation for both power and digital signals that are transmitted from the field side to the logic side.

The MAX22530 device withstands differences in ground potential between the two power domains of up to 5kV_RMS (V_ISO) for up to 60s, and up to 848V_RMS (V_IOWM) for extended periods of time. The MAX22530 is available is 16-pin wide body SOIC package with 8mm of creepage and clearance. The package material has a minimum comparative tracking index (CTI) of 400V to give a group II rating in creepage tables. See Table 4 for certification information.

The MAX22531 and MAX22532 device withstand differences in ground potential between the two power domains of up to 3.75KVRMS (V_ISO) for up to 60s, and up to 445V_RMS (V_IOWM) for extended periods of time. The MAX22531 is available in 20-pin SSOP and MAX22532 is available in 28-pin SSOP with 5.5mm of creepage and clearance. The package material has a minimum comparative tracking index (CTI) of 400V to give a group II rating in creepage tables. See Table 4 for certification information.