It is recommended to decouple both the VDDL and VDDPL supplies with 1μF capacitors in parallel with 0.01μF capacitors to GNDL. Place the 0.01μF capacitors as close to VDDL and VDDPL as possible. The VDDF pin is the integrated DC-DC converter output and it is recommended to decouple it with low-ESR capacitors of 1μF in parallel with 0.01μF to GNDF. Place the 0.01μF capacitor as close to VDDF as possible.
The PCB designer should follow some critical recommendations to get the best performance from the design.
- Keep the input/output traces as short as possible. To keep signal paths low inductance, avoid using vias.
- Have a solid ground plane underneath the signal layer to minimize the noise.
- Keep the area underneath the MAX22530–MAX22532 free from ground and signal planes. Any galvanic or metallic connection between the field side and logic side defeats the isolation.
- Ensure that the decoupling capacitors between VDDL, VDDPL and GNDL, and between VDDF and GNDF are located as close as possible to the IC to minimize inductance.
- Route important signal lines close to the ground plane to minimize possible external influences. On the field-side, it is good practice to separate the ADC input and voltage reference ground AGND from the VDDF reference ground GNDF.
- MAX22531 has two extra AGND pins, and MAX22532 has four extra AGND pins to provide analog ground reference points for the respective AIN_ channels.
The MAX22530–MAX22532 family features an integrated DC-DC converter to generate a nominal 3.1V supply, powering the field side of the MAX22530–MAX22532. The DC-DC converter passes power from the logic side across the isolation barrier through an internal transformer. Due to the isolated nature of the device, the split of the ground planes (GNDL and GNDF) prevents the return current from flowing back to the logic side; thus, causing high-frequency signals to radiate when crossing the isolation barrier. A spread-spectrum option is added to the DC-DC converter to reduce the radiated emissions.
The MAX22530–MAX22532 can meet CISPR 22 and FCC radiated emission standards with proper PCB design. A stitching capacitance of 50pF minimum is recommended to be built into the PCB to pass the CISPR 22 and FCC Class B limits. See Figure 7 and Figure 8.
To achieve optimal radiated emission performance, the following layout guidelines are recommended:
Calculate the stitching capacitance value by using the following equation, where A is the overlapping area between the GNDL and GNDF planes.
C = A × ε0 × εr × d
where,
ε0 = Permittivity of free space (8.854 x 10-12 F/m),
εr = Relative permittivity of the PCB insulation material, and
d = Dielectric thickness between two adjacent layers.
- Adjust the overlapping area (A) or the dielectric thickness (d) to achieve a minimum 50pF stitching capacitance. Make sure that the creepage and clearance between the GNDF plane and the GNDL plane on the same layer as well as between two different layers large enough to meet isolation standards for various applications.
- Multiple GNDL and GNDF vias are recommended to be placed next to the GNDF and GNDL pins to provide a good connection between the stitching capacitor and the device ground pins.
- Apply edge guarding vias to stitch the GNDF and GNDL planes on all layers together to limit the emission from escaping from the PCB edges.
Stitching Capacitance on Internal Layers
MAX22530 Radiated Emission with 90pF Stitching Capacitance, 3-Meter Antenna Distance, Horizontal Scan
MAX22530 Radiated Emission with 90pF Stitching Capacitance, 3-Meter Antenna Distance, Vertical Scan
MAX22531 Radiated Emission with 100pF Stitching Capacitance, 3-Meter Antenna Distance, Horizontal Scan
MAX22531 Radiated Emission with 100pF Stitching Capacitance, 3-Meter Antenna Distance, Vertical Scan