Detailed Description

The MAX22514 IO-Link transceiver integrates high voltage functionality, including one 24V line driver, an integrated DC-DC buck regulator, and 5V and 3.3V linear regulators. The MAX22514 is targeted for IO-Link devices, masters, and industrial switching sensor applications, and can be configured and monitored using a standard SPI interface.

The MAX22514 features an IO-Link transceiver interface capable of operating with voltages up to 36V. This is the industrial standard 24V interface and includes the C/Q input/output, the V24 supply, and ground. The C/Q switching driver is programmable for PNP, NPN, or push-pull mode, features a programmable current limit, slew rate, and pull-up/pull-down currents, and operates over all of the COM1, COM2, and COM3 IO-Link data rates.

The C/Q driver is enabled when TXEN is high and the CQ_EN = 1 in the CQCONFIG register. Toggle the TX input to switch the C/Q output. Alternatively, set the CQ_Q bit in the CONTROL register to set C/Q high or low. See Table 1 and Table 2. C/Q is the logic inverse of the TX input, by default. Set the INVCQ = 1 in the CQCONFIG register to align the TX, C/Q, and RX logic states.

X = Don’t care

X = Don’t care

The C/Q driver features a programmable current limit. Select the current limit by setting the CL[1:0] bits in the CURRLIM register. Current limit thresholds can be set to 50mA (min), 100mA (min), 200mA (min), and 250mA (min). When the load attempts to draw more current than the current limit threshold setting, the C/Q driver actively limits the load current so a higher load current does not flow.

Setting CLDIS = 1 disables active current limiting, resulting in higher load currents. Setting CLDIS = 1 should only be done in PNP mode. Setting CLDIS = 1 in NPN or push-pull modes can damage the device.

The MAX22514 features an autoretry function to mange and limit heating and power dissipation during driver overload conditions.

Set the AUTORETRYEN bit (AUTORETRYEN = 1) in the CURRLIM register to enable autoretry functionality. When autoretry is enabled, the MAX22514 disables the driver after the current limit threshold has been exceeded for the selected blanking time. The driver is disabled for the programmed fixed off-time and is then automatically reenabled. If the overcurrent condition persists, the driver remains on for the blanking time and is then redisabled. This autoretry cycle continues until the overcurrent condition is removed.

Select the blanking time and fixed off-time by setting the CL_BL[1:0] bits and the TAR[1:0] bits respectively in the CURRLIM register.

When charging large capacitive loads or incandescent lamps, ensure that the selected autoretry blanking time is long enough to charge the required load before the driver is disabled.

The C/Q driver is turned off when the driver junction temperature exceeds the +160ºC (typ) driver thermal shutdown temperature. The associated driver fault bits (CQFAULTINT, CQFAULT) in the INTERRUPT and STATUS registers (respectively) are set. If the fault is not masked (CQFAULTM = 0 in the IRQMASK register), IRQ is asserted after the programmed blanking time. Set the CL_BL[1:0] bits in the CURRLIM register to select the blanking time. The driver is automatically reenabled when the driver junction temperature falls below 145ºC (typ).

Although the IO-Link standard defines operation for a supply ranging between 18V to 30V, industrial controllers and sensors in the field commonly operate with supply voltages as low as 9V. The MAX22514 operates with a supply voltage between 8V and 36V. When the V24 supply voltage is above 18V, the C/Q receiver on the MAX22514 supports the standard IO-Link receiver thresholds. When V24 is less than 18V, the MAX22514 scales the C/Q receiver thresholds, allowing receiver functionality down to the lowest supply voltage.

The C/Q receiver can also be configured to detect 5V TTL signal levels. Set the RXTTL bit (RXTTL = 1) in the CQMASTER register to enable TTL thresholds on the C/Q receiver. RXTTL is not set by default.

The MAX22514 features six different pull-up/pull-down current sources/sinks that can be enabled on the C/Q line: a 200µA (typ) weak pull-up and/or pull-down current, a 2mA (min) pull-up or pull-down current, and a 5mA (min) pull-up or pull-down current. Configure and enable the current on C/Q by setting the CQ_PD and CQ_PU bits in the CQCONFIG register and by setting the CQPUD5MA and CQPUD2MA bits in the CQMASTER register. See Table 3.

X = Don’t care

A wake-up event occurs when an IO-Link master forces a level on the C/Q line that is opposite to the set level of the C/Q driver level for 80µs (typ). WU pulses low for 200µs (typ) when the device detects a wake-up pulse on C/Q (Figure 5).

Wake-up detection on the MAX22514 is enabled by default. When a valid wake-up event is detected and the interrupt is not disabled (WUM = 0 in the IRQMASK register), the MAX22514 generates an interrupt and asserts IRQ.

To disable wake-up detection, set the WUDIS bit in the CONTROL register. When WUDIS = 1, the WUINT bit is not set when a wake-up pulse is detected.

The MAX22514 automatically ignores false wake-up events that can sometimes occur as a consequence of driving large capacitive or lamp loads where the time constant of charging is around 80µs. No wake-up event is detected for the duration of the programmed blanking time after the C/Q driver changes logic state.

The MAX22514 can generate an IO-Link master wake-up pulse. To prepare the transceiver to generate a wake-up pulse, set the C/Q driver in receive mode (TXEN = low) and set the TX input high. Set the WUGEN bit in the CQMASTER register to generate the wake-up pulse.

When WUGEN = 1, the MAX22514 samples the voltage level on the C/Q receiver. The device then enables the C/Q driver and pulls the C/Q line to the opposite polarity of the sampled voltage for 80μs (typ). The driver remains enabled and the line is driven back to the original polarity after the wake-up pulse duration. Following the on-time after wake-up delay (tON_WU), the driver is set to high impedance. The MAX22514 continues to ignore signals on TX and TXEN and holds the driver in a high impedance state for the high-impedance time after wake-up delay (t_{DIS_WU}), after which the microcontroller can initiate the EstablishCOM IO-Link communication sequence. See Figure 6.

While the MAX22514 is generating the wake-up pulse, the current limit is automatically set above 500mA and the C/Q slew rates are automatically set to the highest rate. Register settings are not changed during wake-up generation, and programmed current limit and slew rate settings operate normally after the wake-up pulse is generated. These settings do not need to be reprogrammed after a wake-up is generated.

V_CCB is the output of an internal regulator powered by V₂₄ or V₅. V_CCB is powered by V₂₄ until the V₅ voltage exceeds 3.92V (min). After which, V_CCB is powered by V₅. As V₅ is rising, and V_CCB can drop below 5V until V₅ reaches its steady state voltage. V_CCB can be used to drive a small (≤ 10mA) external load.

The RESET/POK pin is a dual function open-drain logic input/output, functioning as a reset input and a power-OK (POK) output.

Drive RESET/POK low to put the MAX22514 in reset mode. The C/Q driver is disabled and the registers are reset to their default state when RESET/POK is driven low. Serial bus communication is available while RESET/POK is low. If the DC-DC has been disabled in the registers (BUCKDIS = 1), the device deasserts RESET/POK 4ms (typ) after RESET/POK is released and all power supplies are valid. If the DC-DC has been enabled, RESET/POK deasserts immediately after being released.

The MAX22514 asserts RESET/POK low when V₂₄ or V₅ voltage falls below their respective UVLO thresholds, or when the DC-DC output voltage falls below 95% of the set voltage (typ). The C/Q driver is disabled and the registers are reset to their default state when RESET/POK is low. Serial bus communication is available while RESET/POK is low. The MAX22514 deasserts RESET/POK 4ms (typ) after all power supplies are valid.

Connect a pull-up resistor between RESET/POK and V_L or V_CCB for normal operation. Connect RESET/POK to the reset input of a microcontroller to use it as a reset signal.

The MAX22514 features a flexible voltage comparator. This comparator monitors the voltage at the V_M input. When the V_M input voltage is below the 858mV (typ) threshold, the VMINT bit in INTERRUPT register is set and IRQ is asserted if not masked (VMINTM = 0 in the IRQMASK register). Note that the VMINT interrupt bit is not cleared when the INTERRUPT register is read while the V_M voltage is below the comparator threshold. This bit is cleared only if the V_M voltage exceeds the threshold voltage during the INTERRUPT read.

V_M can be used to supervise the voltage on V₂₄, PV₂₄, or any other pin.

For example, to monitor the PV₂₄ use a resistor divider between PV₂₄, V_M, and GND to set the minimum PV₂₄ voltage threshold (Figure 8). Calculate the monitored voltage power-OK threshold (V_POK) as:

V_POK = V_{TH_M} x [(R₁ + R₂) / R₂]

Select the resistor values to ensure that V_M does not exceed the 5.5V maximum voltage.

The MAX22514 features an integrated high-efficiency synchronous DC-DC buck regulator with active diode reverse protection, current overload protection, soft start, spread spectrum operation, and an adjustable output voltage. The DC-DC regulator operates with a fixed 1.229MHz (typ) frequency during normal operation. The regulator can be configured to operate in pulse-width modulation (PWM) mode, pulse frequency modulation (PFM) mode, or discontinuous conduction mode (DCM) during normal operation. Select the operating mode by setting the BUCKDCM or BUCKPFM mode bits in the MODE register. The regulator is enabled by default but can be disabled through the serial interface. The DC-DC regulator is supplied from the PV24 voltage to protect against supply inversion. Bypass PV24 to GND with a 1μF capacitor to ensure proper operation for the DC-DC.

The MAX22514 DC-DC buck regulator features soft-start to slowly raise the output voltage when the device is powered up. When the V₂₄ voltage exceeds the 7.5V (typ) UVLO threshold, the DC-DC regulator is turned on, operating in DCM mode. DCM mode allows the DC-DC output to soft-start whether the output voltage is unpowered or prebiased. Internal circuitry slowly ramps the output voltage to 95% of the set voltage within 3.3ms (typ) of the V₂₄ voltage exceeding the UVLO threshold, ending the soft-start sequence. Once soft-start has ended, the regulator switches from DCM mode to the selected mode for normal operation. By default, normal operation is PWM mode. Set the BUCKPFM and/or the BUCKDCM bits in the MODE register to select another operating mode of the DC-DC regulator.

The MAX22514 integrated DC-DC buck regulator can supply loads up to 200mA (typ). The internal reverse-protection active diode between V₂₄ and PV₂₄ has a 200mA average current capability to supply the DC-DC input. Under certain conditions, the internal active diode between the V₂₄ supply and PV₂₄ can reduce the efficiency or reduce the maximum load current. If load currents are such that the current through the active diode exceeds 300mA, connect a Schottky diode between V₂₄ and PV₂₄ to bypass the internal active diode. When a Schottky diode is used, a TVS or varistor on V₂₄ might be necessary to survive hot-plug events.

A Pulse Width Modulation Mode (PWM) DC-DC regulator switches at a fixed frequency, adjusting the duty cycle of the pulses depending on the output power requirements. The maximum duty cycle on the DC-DC regulator is near 100%. Switching noise is easily filtered in PWM mode. The MAX22514 DC-DC regulator operates in PWM mode by default (BUCKDCM = 0 and BUCKPFM = 0 in the MODE register).

In Pulse Frequency Modulation Mode (PFM), the DC-DC converter switches LX with a peak current set to be at least 200mA (typ). LX stops switching when the output voltage exceeds 103% of the set value and starts switching again when the DC-DC output voltage drops to 101% of the set value. Because the switching frequency changes in PFM mode, switching noise is more difficult to filter in PFM mode typically resulting in a higher ripple on the output. PFM mode has the highest efficiency when driving low loads. Set BUCKPFM = 1 and BUCKDCM = 0 in the MODE register to enable PFM mode on the DC-DC regulator.

In Discontinuous Conduction Mode (DCM), the inductor current of the DC-DC regulator can reach zero for a short period during each switching cycle. In this mode, the output voltage is dependent on the input voltage, the inductance in the DC-DC regulator, the switching frequency, and the load. Use DCM mode for low output ripple and high efficiency under light load conditions. The MAX22514 DC-DC regulator operates in DCM mode during soft-start. Set BUCKDCM = 1 in the MODE register (the BUCKPFM bit is ignored, in this case) to enable DCM functionality for normal operation.

The integrated DC-DC buck regulator on the MAX22514 is enabled by default but can be disabled through the serial interface. Set the BUCKDIS bit in the MODE register to disable the DC-DC. If the DC-DC regulator is not used, leave the LX unconnected and connect FB to VCCB.

The output voltage of the DC-DC regulator can be programmed from 2.5V to 12V. Set the output voltage by connecting a resistor divider from the output to FB to GND (Figure 9).

Calculate the output voltage using the following equation:

R₁ = R₂ x (V_OUT /0.9 - 1)

Ensure that R₁ || R₂ ≤ 46kΩ and use ±1% resistors for best accuracy.

The R₁ resistor controls the load regulation on the load step and can also affect the value of the output capacitor to ensure stability of the DC-DC regulator. See Table 4 for R₁ and R₂ values for common DC-DC output voltage settings.

A low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions should be selected. The saturation current (I_SAT) must be high enough ensure that saturation cannot occur below the 440mA maximum current-limit value. Under lower load conditions, smaller inductors can be used.

Small ceramic X7R-grade capacitors are sufficient and recommended to use with the MAX22514 DC-DC regulator. The output capacitor has two functions: filter the square wave generated by the device along with the output inductor and stabilize the device's internal control loop. Capacitor selection depends on the operating conditions and the value of R1 and can affect the stability of the DC-DC regulator.

Table 4 shows the recommended component values for the DC-DC buck regulator for a wide range of typical operating conditions (see the Simplified Application Diagram). Recommended values in the table are designed for <±3% load regulation on a 50% load current step and with minimum inductance. A ±30% tolerance on inductance and a ±20% tolerance on capacitance is expected due to C-V dependence.

The DC-DC regulator uses an internal clock synchronized with the main on-board oscillator that is used to generate other signals and timing. To reduce EMC emission peaks and/or reduce interference between the DC-DC switching circuitry and analog circuitry, the MAX22514 features selectable spread-spectrum functionality for the DC-DC clock. When enabled, the DC-DC clock is randomly changed with a maximum frequency deviation of ±10% (typ).

By default, DC-DC spread spectrum is disabled. Set the BUCKSS bit in the MODE register to enable spread spectrum for the DC-DC.

The DC-DC regulator includes integrated circuitry to protect the regulator during a current overload condition to avoid runaway. When the high-side current exceeds the 400mA (typ) high-side peak current limit (I_{DC_HSLIM}), the high-side switch is disabled. Similarly, when the low-side current exceeds the 200mA (typ) low-side current limit threshold (I_{DC_LSMAX}), the low-side switch is turned off and LX is floating until the next clock cycle, when switching begins again.

The DC-DC regulator features an autoretry sequence (hiccup mode) to protect against fault conditions on the output. After soft-start, if the output voltage of the DC-DC regulator falls below 70% of the set threshold, the regulator is disabled for 22ms (typ) and the BUCKFAULT bit in the STATUS2 register is set. Following the autoretry period, the DC-DC is restarted with soft-start.

If the fault on the output persists, the DC-DC is disabled and the autoretry sequence begins again. If the output voltage rises to 95% of the expected voltage, the DC-DC exits hiccup mode and operates normally.

The BUCKFAULT and BUCKOK bits in the STATUS2 register indicate the state of the DC-DC output. Use these bits to monitor the regulator during operation.

The BUCKOK bit is set when the output voltage is above 95% of the set voltage and the regulator is operating normally. When the DC-DC output voltage falls below 95% of the set voltage, RESET/POK asserts and the BUCKOK bit is 0.

The BUCKFAULT bit is set when regulator is in a fault condition. Fault conditions include current overload, when the output voltage falls below 70% of the set threshold, and/or when the regulator is operating in hiccup mode. The BUCKFAULT bit is cleared automatically when the regulator returns to normal operation.

The MAX22514 monitors the die temperature during normal operation. This temperature can be read through the SPI interface and can be configured to generate a high temperature warning when the temperature rises above a set threshold. This threshold is user programmable.

The MAX22514 uses the same thermal sense circuitry to monitor the die temperature for the default thermal warning and when the programmable thermal warning methods are used. The default thermal warning system features a reduced precision, but faster response times. The programmable thermal ADC features a higher precision but slower functionality.

The high temperature warning can be disabled completely by setting the ADC_CONF bits in the THADC_CFG register.

To protect against thermal damage, the MAX22514 monitors the die temperature during operation. The MAX22514 compares the die temperature to two different thresholds: the warning threshold and the thermal shutdown threshold. By default, the high temperature warning threshold is 150°C.

Enable the programmable thermal warning threshold by setting the ADC_CONF[1:0] bits in the THADC_CFG register to 01. Program the warning threshold by setting the THWRN[5:0] bits in the THADC_THD register. Bits in the THWRN[5:0] bits are binary-coded, with 1 LSB = 3°C and THWARN = 0 at -15C (typ). See Table 5_.

The THERMWINT bit in the INTERRUPT register and the TEMPW bit in the STATUS register are set when the die temperature exceeds the thermal warning threshold. If not masked (THERMWM = 0 in the IRQMASK register), IRQ asserts when the THERWINT bit is set. THERMWINT is cleared when the INTERRUPT register is read, but THERMW is not cleared until the temperature is below the thermal warning threshold hysteresis. No hysteresis is available for the programmable warning threshold mode.

Set the ADC_CONF[1:0] bits in the THAD_CNG register to 10 or 11 to enable ADC thermal monitoring to allow the die temperature to be read over the SPI interface.

Set the ADC_START bit in the THADC_CFG register to start the thermal ADC measurement. The ADC_START bit is cleared and the ADC_EOC bit in the THADC_RES register is set after the manual ADC thermal measurement is completed after 450µs (typ). Measurement results are stored in the THVAL[5:0] bits in the THADC_RES register. Measurements are binary-coded, 1 LSB = 3C (typ) and THVAL = 0 at -15C (typ). Thermal ADC measurements range from -15C to 174C. See Table 5_.

Thermal warning functionality is disabled when manual ADC thermal monitoring is enabled. Ignore the THERMW bit in the STATUS register and mask the thermal warning interrupt (THERMWINT in the INTERRUPT register) by setting the THERMWM = 1 in the IRQMASK register.

The MAX22514 is internally protected against reverse polarity miswiring on the V₂₄, C/Q, and GND pins. Any combination of these pins can be connected to a DC voltage in the range of -36V to +36V. Shorts to these voltages result in a current flow of less than 500µA. Note that the maximum voltage between any pins should not exceed the Absolute Maximum Ratings.

The MAX22514 enters thermal shutdown when the average die temperature exceeds the +170°C (typ) thermal shutdown threshold. The C/Q driver, the DC-DC regulator, and the V₅ and V₃₃ regulators are disabled when the device is in thermal shutdown. The MAX22514 exits thermal shutdown when the average die temperature falls below the 20°C (typ) thermal shutdown hysteresis. Thermal shutdown is present regardless of the method of high temperature warning utilized and cannot be disabled.

The MAX22514 performs an ongoing check of all register bits. A register is corrupted when the value is changed by an external event (for example, an ESD discharge, etc). When a corrupt register bit is detected, the CORR_REG bit in the STATUS register is set, the NOTREADY bit in the INTERRUPT register is set, and the MAX22514 asserts the IRQ output. The C/Q driver is disabled when the NOTREADY bit is set.

The microcontroller must rewrite correct values to all of the registers after the CORR_REG bit has been set. The CORR_REG bit is automatically cleared when the serial interface control registers have been rewritten to their pre-event cycle values. Once the CORR_REG bit is cleared, read the INTERRUPT register to clear the NOTREADY bit and deassert IRQ.

The MAX22514 supports full-duplex SPI communication at speeds up to 12MHz. The master must generate clock and data signals in SPI MODE0 (clock polarity CPOL = 0 and clock phase CPHA = 0) to communicate with the MAX22514. The SPI interface is not available when V₅ falls below 4.26V or when V_L is below 2.5V.

Figure 10 shows a single-cycle WPI write command and Figure 11 shows a single-cycle SPI read command.