8 Narrow SOIC
| Package Code | S8MS+24 |
| Outline Number | 21-0041 |
| Land Pattern Number | 90-0096 |
| Thermal Resistance, Four Layer Board: | |
| Junction-to-Ambient (θJA) | 172.80ºC/W |
| Junction-to-Case Thermal Resistance (θJC) | 67.60ºC/W |
8 Wide SOIC
| Package Code | W8MS+7 |
| Outline Number | 21-100415 |
| Land Pattern Number | 90-100146 |
| Thermal Resistance, Four Layer Board: | |
| Junction-to-Ambient (θJA) | 88.10ºC/W |
| Junction-to-Case Thermal Resistance (θJC) | 42.40ºC/W |
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Power Supply Input for Side A. Bypass VDDA to GNDA with a 0.1μF ceramic capacitor as close as possible to the pin.Logic Input 1 on Side B.Logic Output 1 on Side B.Logic Input 2 on Side A.Ground Reference for Side A.Ground Reference for Side B.Logic Output 2 on Side B.Power Supply Input for Side B. Bypass VDDB to GNDB with a 0.1μF ceramic capacitor as close as possible to the pin.