Detailed Description

The MAX22_2_ are a family of 2-channel reinforced ultra-low-power digital isolators. The MAX22_2_ consume ultra-low power not only in DC but also across the entire operating speed range up to 10Mbps. The family offers two unidirectional channel configurations to accommodate any 2-channel design.

The MAX22_20 feature two channels transferring digital signals in one direction. The MAX22_21 have one channel to transmit data in one direction and the other channel to transmit in the opposite direction.

The MAX22420/1 are available in an 8-pin narrow-body SOIC package with 4mm creepage and clearance and are rated up to 3kV_RMS. The MAX22820/1 are available in an 8-pin wide-body SOIC package with 8mm creepage and clearance and are rated up to 5kV_RMS. This family of digital isolators offers ultra-low-power operation, high electromagnetic interference (EMI) immunity, and stable temperature performance through Analog Devices’ proprietary process technology. The devices isolate different ground domains and block high-voltage/high-current transients from sensitive or human interface circuitry.

The family of devices has a maximum data rate of 10Mbps and can be ordered with two glitch filter options and default-high or default-low outputs. The default is the state the output assumes when the input is open circuit. The B/E versions have 70ns (typ) glitch filter and C/F versions have 29ns (typ) glitch filter. The devices have two supply inputs (V_DDA and V_DDB) that independently set the logic levels on either side of device. V_DDA and V_DDB are referenced to GNDA and GNDB, respectively. The family also features a refresh circuit to ensure output accuracy when an input remains in the same state indefinitely.

The MAX22_2_ provide reinforced galvanic isolation for digital signals that are transmitted between two ground domains. The MAX22420/1 withstand differences of up to 3kV_RMS for up to 60 seconds, and up to 630V_PEAK of continuous isolation. The MAX22820/1 withstand differences of up to 5kV_RMS for up to 60 seconds, and up to 1200kV_PEAK of continuous isolation.

The wide supply voltage range of both V_DDA and V_DDB allows the family of devices to be used for level translation in addition to isolation. V_DDA and V_DDB can be independently set to any voltage from 1.71V to 5.5V. The supply voltage sets the logic level on the corresponding side of the isolator.

Each channel of the devices is unidirectional; it only passes data in one direction, as indicated in the Functional Diagrams. Each device features two unidirectional channels that operate independently with guaranteed data rates from DC up to 10Mbps. The output driver of each channel is push-pull, eliminating the need for pullup resistors. The outputs are able to drive both TTL and CMOS logic inputs.

The V_DDA and V_DDB supplies are both internally monitored for undervoltage conditions. Undervoltage events can occur during power-up, power-down, or during normal operation due to a sagging supply voltage. When an undervoltage condition is detected on the output supply, the outputs go to high-Z regardless of the state of the inputs. When an undervoltage condition is detected on the input supply, the outputs go to default regardless of the state of the inputs as seen in Table 3. During the output supply rises above the UVLO (Powered), the output transitions from high-Z to default state for a short period of time before becoming valid. During the output supply drops below the UVLO (Undervoltage), the output transitions to high-Z immediately. Figure 2 shows the output UVLO to output valid and input UVLO to output default timing diagrams. Figure 3 through Figure 6 show the behavior of the outputs during power-up and power-down.

Damage to the IC can result in a low-resistance path to ground or to the supply and, without current limiting, the devices can dissipate excessive amounts of power. Excessive power dissipation can damage the die and result in damage to the isolation barrier, potentially causing downstream issues. Table 4 shows the safety limits for the MAX22_2_.

The maximum safety temperature (T_S) for the device is the 150°C maximum junction temperature specified in the Absolute Maximum Ratings. The power dissipation (P_D) and junction-to-ambient thermal impedance (θ_JA) determine the junction temperature. Thermal impedance values (θ_JA and θ_JC) are available in the Package Information section and power dissipation calculations are discussed in the Calculating Power Dissipation section. Calculate the junction temperature (T_J) as:

T_J = T_A + (P_D x θ_JA)

Figure 7 shows the thermal derating curves for safety limiting the power of the device. Figure 8 shows the thermal derating curve for safety limiting the current of the device. Ensure that the junction temperature does not exceed 150°C.