The family of devices does not require special power-supply sequencing. The logic levels are set independently on either side by VDDA and VDDB. Each supply can be present over the entire specified range regardless of the level or presence of the other supply.
To reduce ripple and the chance of introducing data errors, bypass VDDA and VDDB with 0.1μF low-ESR ceramic capacitors to GNDA and GNDB, respectively. Place the bypass capacitors as close to the power supply input pins as possible.
The PCB designer should follow some critical recommendation in order to get the best performance from the design.
- Keep the input/output traces as short as possible. To keep signal paths low inductance, avoid using vias.
- Have a solid ground plane underneath the high-speed signal layer.
- Keep the area underneath the devices free from ground and signal planes. Any galvanic or metallic connection between the field-side and logic-side defeats the isolation.
The required current for a given supply (VDDA or VDDB) can be estimated by summing the current required for each channel. The supply current for a channel depends on whether the channel is an input or an output, the channel’s data rate, and the capacitive or resistive load if it is an output. The typical current for an input or output at any data rate can be estimated from the graphs in Figure 9 and Figure 10. Note that the data in Figure 9 and Figure 10 are extrapolated from the supply current measurements in a typical operating condition.
The total current for a single channel is the sum of the no load current (shown in Figure 9 and Figure 10), which is a function of voltage and data rate, and the load current, which depends on the type of load. Current into a capacitive load is a function of the load capacitance, the switching frequency, and the supply voltage.
ICL = CL × fSW × VDD
where:
ICL is the current required to drive the capacitive load.
CL is the load capacitance on the isolator’s output pin.
fSW is the switching frequency (bits per second/2).
VDD is the supply voltage on the output side of the isolator.
Current into a resistive load depends on the load resistance, the supply voltage and the average duty cycle of the data waveform. The DC load current can be conservatively estimated by assuming the output is always high.
IRL = VDD ÷ RL
where:
IRL is the current required to drive the resistive load.
VDD is the supply voltage on the output side of the isolator.
RL is the load resistance on the isolator’s output pin.
Example (shown in Figure 11): A MAX22421C is operating with VDDA = 2.5V, VDDB = 3.3V, channel 1 operating at 2Mbps with a 15pF capacitive load, and channel 2 operating at 10Mbps with a 10kΩ resistive load. See Table 5 and Table 6 for VDDA and VDDB supply-current calculation worksheets.
VDDA must supply:
Total current for side A = 454.8μA (typ)
VDDB must supply:
Total current for side B = 350.4μA (typ)
 |  |
| SIDE A | VDDA = 2.5V | |||||
|---|---|---|---|---|---|---|
| CHANNEL | IN/OUT | DATA RATE (Mbps) | LOAD TYPE | LOAD | NO LOAD CURRENT (μA) | LOAD CURRENT (μA) |
| 1 | OUT | 2 | Capacitive | 15pF | 23.93 | 2.5V x 1MHz x 15pF = 37.5μA |
| 2 | IN | 10 | 393.35 | |||
| Total: 454.8μA | ||||||
| SIDE B | VDDB = 3.3V | |||||
|---|---|---|---|---|---|---|
| CHANNEL | IN/OUT | DATA RATE (Mbps) | LOAD TYPE | LOAD | NO LOAD CURRENT (μA) | LOAD CURRENT (μA) |
| 1 | IN | 2 | 82.92 | |||
| 2 | OUT | 10 | Resistive | 10kΩ | 102.49 | 3.3V/10kΩ x 0.5 = 165μA |
| Total: 350.4μA | ||||||