| Package Code | T2444+4C |
| Outline Number | 21-0139 |
| Land Pattern Number | 90-0022 |
| Thermal Resistance, Single-Layer Board: | |
| Junction to Ambient (θJA) | 48°C/W |
| Junction to Case (θJC) | 3°C/W |
| Thermal Resistance, Four-Layer Board: | |
| Junction to Ambient (θJA) | 36°C/W |
| Junction to Case (θJC) | 3°C/W |
data-opMAX22088GTG%2B
data-opMAX22088GTG%2BT
Active Inductor Bypass Capacitor Connection. For 57.6kbps operation, connect a 100nF ceramic capacitor between CAPN and HNA. Connect CAPN to HNA when the Active Inductor is not used. See the Active Inductor section for more information.Active Inductor Bypass Capacitor Connection. For 57.6kbps operation, connect a 100nF ceramic capacitor between CAPN and HNA. Connect HNA to CAPN when the Active Inductor is not used.Active Inductor Bypass Capacitor Connection. Connect a 1μF ceramic capacitor in series with a 180kΩ resistor between CAPP and HPA. In parallel, connect an additional 100nF ceramic capacitor between CAPP and HPA for 57.6kbps operation. Connect HPA to CAPP when the Active Inductor is not used.Active Inductor Bypass Capacitor Connection. Connect a 1μF ceramic capacitor in series with a 180kΩ resistor between CAPP and HPA. In parallel, connect an additional 100nF ceramic capacitor between CAPP and HPA for 57.6kbps operation. Connect CAPP to HPA when the Active Inductor is not used. See the Active Inductor section for more information.Ground Reference. See the Layout Recommendations section for more information.LDO Power Output. Bypass VCC to GND with a 1µF (min) ceramic capacitor as close to the device as possible. VCC is able to supply up to 70mA (max) of current to external loads. See the Internal Voltage Regulator section for more information.Active Inductor Power Output. Bypass VRAW to GND with a 100μF (min) capacitor to drive loads less than 70mA (max). Bypass VRAW to GND with a 200μF (min) capacitor to drive loads more than 70mA (max). See the VRAW Voltage Output section for more information.Exposed pad. Connect EP to GND.Home Bus Data Input and Output. Connect BIO to Home Bus through an external 2.2μF capacitor in series with a 4.7Ω resistor for 57.6kbps operation. See the Operation of MAX22088 Transceiver section for more information.Power Supply Input from Home Bus. Connect HN to GND when the Active Inductor is not used. See the Power Supply section for more information.Power Supply Input from Home Bus. Connect HP to VRAW when the Active Inductor is not used. See the Power Supply section for more information.Home Bus Data Input and Output. Connect AIO to Home Bus through an external 2.2μF capacitor in series with a 4.7Ω resistor for 57.6kbps operation. See the Operation of MAX22088 Transceiver section for more information.Switched Bus Termination. Connect a resistor between TERM and BIO to adjust Home Bus cable termination for better signal quality. See the Dynamic Cable Termination section for more information.Leading Edge Data Threshold. See the Receiver Thresholds section for more information.Trailing Edge Data Threshold. See the Receiver Thresholds section for more information.Open-Drain Data Output. Connect a pullup resistor to the logic voltage supply.Data InputBus Reset Control Input. See the RST (Reset) Functionality section for more information.LDO Enable Input. Connect EN to VRAW to enable the internal voltage regulator. Connect EN to GND to disable the internal voltage regulator.High Pass Filter Enable Input. Connect HPEN to GND to enable the internal high pass filter on receiver input. Connect HPEN to VCC to disable the internal high pass filter. Do not leave HPEN unconnected. See the High Pass Filter section for more information.Slew Rate Adjustment Input. Connect SRA to GND through a resistor to adjust the slew rate of the AIO and BIO transmit edges. See the Transmit Slew Rate Adjustment section for more information.Not Connected