Package Information

64 LGA

Package Code	L649A9M+1
Outline Number	21-100274
Land Pattern Number	90-100096
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ_JA)	23.4°C/W
Junction to Case (θ_JC)	7.0°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

data-opMAX22000ALB%2BT

data-opMAX22000ALB%2B

Positive High-Voltage Supply for the Output Path. Bypass to AGND with a minimum of 1µF ceramic capacitor as close to the device as possible.Positive Transmit Output. Connect to the anode of an external diode.Negative Transmit Output. Connect to the cathode of another external diode.Negative High-Voltage Supply for the Output Path. Bypass to AGND with a minimum of 1µF ceramic capacitor as close to the device as possible.Positive High-Voltage Supply for the Input Paths. Bypass to AGND with a minimum of 1µF ceramic capacitor as close to the device as possible.Analog GroundAnalog Input 1. In analog output current mode, the positive input of the current sense feedback amplifier. In all other modes, either the positive input of a current sense to the ADC with AI2, or a voltage sense to the ADC.Analog Input 2. In analog output current mode, the negative input of the current sense feedback amplifier. In all other modes, either the negative input of a current sense to the ADC with AI1, or a voltage sense to the ADC.Analog Input 3. In analog output voltage mode, the input to the voltage sense feedback amplifier. In all other modes, a high-voltage sense to the ADC.Analog Input 4. A high-voltage sense to the ADC.Analog Input 5. Along with AI6, a positive voltage input of a differential pair to the ADC.Not Connected. Do not connect.Analog Input 6. Along with AI5, a negative voltage input of a differential pair to the ADC.Auxiliary Input 1. First of two auxiliary inputs to the ADC.Auxiliary Input 2. Second of two auxiliary inputs to the ADC.Negative High-Voltage Supply for the Input Paths. Bypass to AGND with a minimum of 1µF ceramic capacitor to AGND.Reference Noise Reduction. Connect a 0.1µF ceramic capacitor to AGND to reduce wideband noise. Leave unconnected if not used.Analog Power Supply. Connect a 2.7V to 3.6V source here. Bypass each pin to AGND with a minimum of 1µF ceramic capacitor as close to the device as possible.Voltage Reference Output. Bypass to AGND with a minimum of 1µF ceramic capacitor in parallel with a 0.1µF ceramic capacitor as close to the device as possible.ADC Buffered Reference Voltage Output. Bypass to AGND with a minimum of 4.7µF ceramic capacitor as close to the device as possible.ADC External Voltage Reference Input. If used to supply an external reference, bypass to AGND with a minimum 0.01µF ceramic capacitor as close to the device as possible. If unused, connect to AGND.General Purpose Digital Input/Output 5General Purpose Digital Input/Output 4General Purpose Digital Input/Output 3General Purpose Digital Input/Output 2General Purpose Digital Input/Output 1General Purpose Digital Input/Output 0Digital GroundDigital Power Supply. Connect a 2.7V to 3.6V source here. Bypass each pin to DGND with a minimum 1µF ceramic capacitor as close to the device as possible.ADC Regulator Bypass. Bypass to DGND with a minimum 0.22µF ceramic capacitor.External Clock Input (Optional). Use a 7.3728MHz frequency to match internal clock and to meet filter requirements. Connect to DGND if unused.ADC Synchronization Input. SYNC resets the ADC modulator and digital filters. If used, connect the SYNC pins of multiple MAX22000 in parallel. If unused, connect to DGND.Data Ready Output. Asserts active low when a new ADC conversion result is available. Reading a sample resets RDY inactive high. RDY is always driven.Interrupt Output. Open Drain, asserts active low. Functionality controlled by registers GEN_INT and GEN_INTEN Reset Input. When asserted active low, reconfigures all registers to their power-on default states, analog output goes high impedance, analog inputs power down, and ADC conversion stops.SPI Serial Data Output. Three-states when CS is inactive high. Connect to SPI MISO signal.SPI Serial Data Input. Connect to SPI MOSI signal.SPI Serial Clock Input. Connect to SPI interface CLK signal.SPI Slave Select Input. The SPI interface responds only when CS is active low.DAC Load Input. When asserted active low, transfers the contents of the DAC data register and updates the DAC output. LDAC is ignored while RST is active low. Connect to DGND if not used.DAC Regulator Bypass. Bypass to DVDD with a minimum of 1µF ceramic capacitor.DAC Analog Ground.DAC Buffered Reference Voltage Output. Bypass to AGND with a minimum of 100pF ceramic capacitor as close to the device as possible.DAC External Voltage Reference Input. If used to supply an external reference, bypass to AGND with a minimum of 0.01µF ceramic capacitor as close to the device as possible. If unused, connect to AGND.Highway Addressable Remote Transducer (HART) Input. Please refer to HART_IN description.Transmit Output Buffer Feedback. Please refer to FB pin description.Exposed Pad. Exposed pads are on the bottom of the package. Connect to HVSS. Solder exposed pad area to HVSS with multiple vias for best thermal performance.