Functional Diagram
Application Block Diagram
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
50Ω
5V to 28V
5V TO 28V
100pF
100pF
1µF
1µF
Analog Input 1. In analog output current mode, the positive input of the current sense feedback amplifier. In all other modes, either the positive input of a current sense to the ADC with AI2, or a voltage sense to the ADC.
AI1
AI1
Analog Input 3. In analog output voltage mode, the input to the voltage sense feedback amplifier. In all other modes, a high-voltage sense to the ADC.
AI3
AI3
Auxiliary Input 1. First of two auxiliary inputs to the ADC.
AUX1
AUX1
Auxiliary Input 2. Second of two auxiliary inputs to the ADC.
AUX2
AUX2
Analog Input 4. A high-voltage sense to the ADC.
AI4
AI4
Positive Transmit Output. Connect to the anode of an external diode.
AOP
AOP
Negative Transmit Output. Connect to the cathode of another external diode.
AON
AON
Analog Input 2. In analog output current mode, the negative input of the current sense feedback amplifier. In all other modes, either the negative input of a current sense to the ADC with AI1, or a voltage sense to the ADC.
AI2
AI2
Negative High-Voltage Supply for the Output Path. Bypass to AGND with a minimum of 1µF ceramic capacitor as close to the device as possible.
HVSSO
HVSSO
Negative High-Voltage Supply for the Input Paths. Bypass to AGND with a minimum of 1µF ceramic capacitor to AGND.
HVSS
HVSS
Analog Ground
AGND
AGND
Digital Ground
DGND
DGND
SPI Slave Select Input. The SPI interface responds only when CS is active low.
CS
CS
GPIO[5:0]
GPIO[5:0]
DAC Load Input. When asserted active low, transfers the contents of the DAC data register and updates the DAC output. LDAC is ignored while RST is active low. Connect to DGND if not used.
LDAC
LDAC
DAC Analog Ground.
AGND_DAC
AGND_DAC
DAC Analog Ground.
AGND_DAC
AGND_DAC
Analog Input 5. Along with AI6, a positive voltage input of a differential pair to the ADC.
AI5
AI5
Analog Input 6. Along with AI5, a negative voltage input of a differential pair to the ADC.
AI6
AI6
SPI Serial Clock Input. Connect to SPI interface CLK signal.
SCLK
SCLK
SPI Serial Data Input. Connect to SPI MOSI signal.
SDI
SDI
SPI Serial Data Output. Three-states when CS is inactive high. Connect to SPI MISO signal.
SDO
SDO
Interrupt Output. Open Drain, asserts active low. Functionality controlled by registers GEN_INT and GEN_INTEN
INT
INT
Reset Input. When asserted active low, reconfigures all registers to their power-on default states, analog output goes high impedance, analog inputs power down, and ADC conversion stops.
RST
RST
Data Ready Output. Asserts active low when a new ADC conversion result is available. Reading a sample resets RDY inactive high. RDY is always driven.
RDY
RDY
ADC Synchronization Input. SYNC resets the ADC modulator and digital filters. If used, connect the SYNC pins of multiple MAX22000 in parallel. If unused, connect to DGND.
SYNC
SYNC
External Clock Input (Optional). Use a 7.3728MHz frequency to match internal clock and to meet filter requirements. Connect to DGND if unused.
CLK
CLK
Voltage Reference Output. Bypass to AGND with a minimum of 1µF ceramic capacitor in parallel with a 0.1µF ceramic capacitor as close to the device as possible.
REF_OUT
REF_OUT
Reference Noise Reduction. Connect a 0.1µF ceramic capacitor to AGND to reduce wideband noise. Leave unconnected if not used.
NR
NR
REF_ADC_EXT
REF_ADC_EXT
ADC Buffered Reference Voltage Output. Bypass to AGND with a minimum of 4.7µF ceramic capacitor as close to the device as possible.
REF_ADC
REF_ADC
ADC Regulator Bypass. Bypass to DGND with a minimum 0.22µF ceramic capacitor.
BYP_ADC
BYP_ADC
`
`
0.22μF
0.22μF
4.7µF
4.7µF
1µF
1µF
-5V to -24V
-5V TO -24V
2.7V to 3.6V
2.7V TO 3.6V
1µF
1µF
1µF
1µF
2.7V to 3.6V
2.7V TO 3.6V
1µF
1µF
1µF
1µF
0.1µF
0.1µF
µC
µC
4.7kΩ
4.7kΩ
Analog Input
ANALOG INPUT
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
Return
RETURN
Analog Input
ANALOG INPUT
Analog Input
ANALOG INPUT
CONFIGURABLE Analog I/O
CONFIGURABLE ANALOG I/O
Positive High-Voltage Supply for the Output Path. Bypass to AGND with a minimum of 1µF ceramic capacitor as close to the device as possible.
HVDDO
HVDDO
Positive High-Voltage Supply for the Input Paths. Bypass to AGND with a minimum of 1µF ceramic capacitor as close to the device as possible.
HVDD
HVDD
Analog Power Supply. Connect a 2.7V to 3.6V source here. Bypass each pin to AGND with a minimum of 1µF ceramic capacitor as close to the device as possible.
AVDD
AVDD
Digital Power Supply. Connect a 2.7V to 3.6V source here. Bypass each pin to DGND with a minimum 1µF ceramic capacitor as close to the device as possible.
DVDD
DVDD
DAC External Voltage Reference Input. If used to supply an external reference, bypass to AGND with a minimum of 0.01µF ceramic capacitor as close to the device as possible. If unused, connect to AGND.
REF_DAC_EXT
REF_DAC_EXT
DAC Buffered Reference Voltage Output. Bypass to AGND with a minimum of 100pF ceramic capacitor as close to the device as possible.
REF_DAC
REF_DAC
DAC Regulator Bypass. Bypass to DVDD with a minimum of 1µF ceramic capacitor.
BYP_DAC
BYP_DAC
Highway Addressable Remote Transducer (HART) Input. Please refer to HART_IN description.
HART_IN
HART_IN
Transmit Output Buffer Feedback. Please refer to FB pin description.
FB
FB
100pF
100pF
47pF
47pF
24.9kΩ
24.9kΩ
0.1µF
0.1µF
MAX22000
MAX22000
DFLS1150 or equivalent
DFLS1150
OR EQUIVALENT
Note: For INternal Reference Only
NOTE: FOR
INTERNAL
REFERENCE ONLY
Note: For INternal Reference Only
NOTE: FOR
INTERNAL
REFERENCE ONLY
