Electrical Characteristics

Electrical Characteristics
(V_AVDD = V_DVDD = +2.7V to +3.6V, V_HVDD = V_HVDDO = +18.0V; V_HVSS = V_HVSSO = -18.0V, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at V_AVDD = V_DVDD = 3.3V, V_HVDD = V_HVDDO = +18.0V, V_HVSS = V_HVSSO = -18.0V, T_A = +25°C.) (Note 1)
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
ANALOG OUTPUT VOLTAGE MODE
Output Voltage Range	V_OUT	12.5V setting, DAC full-scale range (Note 2)		±12.5		V
		12.5V setting, linear range (Note 2, Note 3)	-10.5		+10.5
		25V setting (Note 2)		+25
Dropout Voltage		V_HVDDO = +13V, sourcing 25mA, measured between HVDDO and AOP, gain compression <1%			0.85	V
Dropout Voltage		V_HVDDO = -13V, sinking 25mA, measured between AON and HVSSO, gain compression <1%			0.85	V
Output Current Protection		Output shorted to HVDDO or HVSSO, threshold current (Note 4)		50		mA
Output Current Protection		Output shorted to HVDDO or HVSSO, average current (Note 4)		13		mA
AOP, AON High Impedance Leakage Current		Measured at the combined output after the external diodes			±0.5	µA
Offset Error	V_OFF	T_A = +25°C before calibration			±150	mV
Offset Calibration Range				±12.5		V
Offset Calibration Resolution				95		µV
Offset Drift		T_A = +50°C ± 50°C with internal reference (Note 5)		±18		µV/°C
Gain Error		T_A = +25°C before calibration	0		4	%
Gain Calibration Range				0 to 100		%
Gain Calibration Resolution				4		ppm
Gain Drift		T_A = +50°C ± 50°C with internal reference (Note 5)		±3.3		ppm/°C
INL Error	INL	T_A = +25°C			±300	µV
INL Drift		T_A = +50°C ± 50°C (Note 5)		±3		µV/°C
Output Noise	V_N	10kHz bandwidth		85		µV_RMS
Supply Rejection Ratio	PSRR	DC, 12.5V setting, V_OUT = 0V, V_HVDD = V_HVDDO = +5V to +24V		120		dB
Supply Rejection Ratio	PSRR	DC, 12.5V setting, V_OUT = 0V, V_HVSS = V_HVSSO = -24V to -5V		115		dB
Load Regulation		-10mA ≤ I_LOAD ≤ +10mA, measured at V_OUT = -10.5V and V_OUT = +10.5V, output change due to self-heating excluded		±0.1		mV
AI3 Headroom		From V_HVSS (Note 3)	2.5			V
AI3 Headroom		From V_HVDD (Note 3)	2.5			V
AI3 Input Current		(Note 5)			±20	nA
Settling Time		12.5V setting, resistive load from 1kΩ to 10MΩ; settling to 1% for V_OUT = 0V to +10.5V or 0V to -10.5V		0.2		ms
Settling Time		12.5V setting, capacitive load up to 1µF; settling to 1% for V_OUT = 0V to +10.5V or 0V to -10.5V		1		ms
Bandwidth of 25V Setting		-3dB bandwidth from HART_IN to output, 25V setting, load as depicted in Figure 3		10		kHz
ANALOG OUTPUT CURRENT MODE
Output Current Range	I_OUT	25mA setting, R_SENSE = 50Ω, DAC full-scale range (Note 6)		±25		mA
		25mA setting, R_SENSE = 50Ω, linear range (Note 3, Note 6)	-21		+21
		2.5mA setting, R_SENSE = 50Ω, DAC full-scale range (Note 6)		±2.5
		2.5mA setting, R_SENSE = 50Ω, linear range (Note 3, Note 6)	-2.1		+2.1
Dropout Voltage		Sourcing 25mA, measured between HVDDO and AOP, gain compression <1%			0.85	V
Dropout Voltage		Sinking 25mA, measured between AON and HVSSO, gain compression <1%			0.85	V
Offset Error	I_OFF	25mA setting, T_A = +25°C before calibration			±300	µA
Offset Error	I_OFF	2.5mA setting, T_A = +25°C before calibration			±30	µA
Offset Calibration Range		25mA setting		±25		mA
Offset Calibration Range		2.5mA setting		±2.5		mA
Offset Calibration Resolution		25mA setting		200		nA
Offset Calibration Resolution		2.5mA setting		20		nA
Offset Drift		25mA setting, T_A = +50°C ± 50°C with internal reference (Note 5)		±36		nA/°C
Offset Drift		2.5mA setting, T_A = +50°C ± 50°C, with internal reference (Note 5)		±4		nA/°C
Gain Error		25mA setting, T_A = +25°C before calibration	0		4	%
Gain Calibration Range		All settings		0 to 100		%
Gain Calibration Resolution		All settings		4		ppm
Gain Drift		25mA setting, T_A = +50°C ± 50°C, with internal reference (Note 5)		±3.2		ppm/°C
INL Error	INL	25mA setting, T_A = +25°C			±600	nA
INL Drift		25mA setting, T_A = +50°C ± 50°C (Note 5)		±6		nA/°C
Output Noise	I_N	25mA setting, 10kHz bandwidth		270		nA_RMS
Output Noise	I_N	2.5mA setting, 10Hz bandwidth		25		nA_p-p
Supply Rejection	PSR	DC, 25mA setting, V_HVDD = V_HVDDO = +5V to +24V		10		nA/V
Supply Rejection	PSR	DC, 25mA setting, V_HVSS = V_HVSSO = -24V to -5V		10		nA/V
AI1, AI2 Headroom		From V_HVSS (Note 3)	2.5			V
AI1, AI2 Headroom		From V_HVDD (Note 3)	2.5			V
AI1, AI2 Input Current		(Note 5)			±20	nA
Common-Mode Rejection	CMR	AI1, AI2 in CSA mode, V_AI1 = V_AI2 = V_CM, V_CM = -16V to +16V			0.5	µA/V
AI1 and AI2 Differential Input Range		AI1, AI2 in CSA mode		±1.25		V
AI1 and AI2 Differential Input Impedance		AI1, AI2 in CSA mode		100		MΩ
Settling Time		Resistive load up to 250Ω; settling to 1% for I_OUT = 0mA to +21mA or 0mA to -21mA		0.5		ms
		Resistive load up to 750Ω; settling to 1% for I_OUT = 0mA to +21mA or 0mA to -21mA		1.0
		Inductive load up to 1mH; settling to 1% for I_OUT = 0mA to +21mA or 0mA to -21mA		0.5
ANALOG INPUT VOLTAGE MODE (AI1 TO AI4)
Headroom		From V_HVSS (Note 3)	2.5			V
Headroom		From V_HVDD (Note 3)	2.5			V
Input Voltage Range	V_IN	ADC full-scale range		±12.5		V
Input Voltage Range	V_IN	Linear range (Note 3)	-10.5		+10.5	V
Offset Error	V_OFF	T_A = +25°C before calibration			±25	mV
Offset Calibration Range				±12.5		V
Offset Calibration Resolution				3		µV
Offset Drift		T_A = +50°C ± 50°C with internal reference (Note 5)		±12		µV/°C
Gain Error		T_A = +25°C before calibration			±4	%
Gain Calibration Range				0 to 200		%
Gain Calibration Resolution				0.1		ppm
Gain Drift		T_A = +50°C ± 50°C with internal reference (Note 5)		±2.2		ppm/°C
INL Error	INL	T_A = +25°C			±600	µV
INL Drift		T_A = +50°C ± 50°C (Note 5)		±2.4		µV/°C
Input Voltage Noise	V_N	ADC sample rate is 57.6ksps, ADC mode is Continuous		85		µV_RMS
Input Current		(Note 5)			±20	nA
Supply Rejection Ratio	PSRR	DC, V_HVDD = +5V to +24V		100		dB
Supply Rejection Ratio	PSRR	DC, V_HVSS = -24V to -5V		100		dB
50/60Hz Normal Mode Rejection		DCHNL_RATE[3:0] = 0b0010, 0b0011, 0b0100, 0b0101	87			dB
50/60Hz Normal Mode Rejection		DCHNL_RATE[3:0] = 0b0000, 0b0001	75			dB
Open/Short Detector Resistance		From any AI1 through AI6 to HVDD		2		MΩ
Open/Short Detector Resistance		From any AI1 through AI6 to AGND		2		MΩ
Settling Time		V_IN changes from 0V to +10.5V or 0V to -10.5V, digital output reaches 1% of final value, ADC sample rate is 57.6ksps, ADC mode is Continuous		100		µs
ANALOG INPUT VOLTAGE MODE – PGA (AI5, AI6)
Headroom		From V_HVSS (Note 3)	2.5			V
Headroom		From V_HVDD (Note 3)	2.5			V
Input Voltage Range	V_IN	25V setting, ADC full-scale range		±25		V
		25V setting, linear range (Note 3)	-21		21
		2.5V setting, ADC full-scale range		±2.5
		2.5V setting, linear range (Note 3)	-2.1		+2.1
		500mV setting, ADC full-scale range		±500		mV
		500mV setting, linear range (Note 3)	-420		+420
		250mV setting, ADC full-scale range		±250
		250mV setting, linear range (Note 3)	-210		+210
		125mV setting, ADC full-scale range		±125
		125mV setting, linear range (Note 3)	-105		+105
Offset Error	V_OFF	25V setting, T_A = +25°C before calibration			±25	mV
		2.5V setting, T_A = +25°C before calibration		±300		µV
		500mV setting, T_A = +25°C before calibration			±500
		250mV setting, T_A = +25°C before calibration		±30
		125mV setting, T_A = +25°C before calibration		±15
Offset Calibration Range		25V setting		±25		V
		2.5V setting		±2500		mV
		500mV setting		±500
		250mV setting		±250
		125mV setting		±125
Offset Calibration Resolution		25V setting		6		µV
		2.5V setting		0.6
		500mV setting		0.12
		250mV setting		0.06
		125mV setting		0.03
Offset Drift		25V setting, T_A = +50°C ± 50°C with internal reference (Note 5)		±12		μV/°C
Offset Drift		500mV setting, T_A = +50°C ± 50°C with internal reference (Note 5)		±600		nV/°C
Gain Error		All voltage settings, T_A = +25°C before calibration			±4	%
Gain Calibration Range				0 to 200		%
Gain Calibration Resolution				0.1		ppm
Gain Drift		25V setting, T_A = +50°C ± 50°C with internal reference (Note 5)		±2.2		ppm/°C
Gain Drift		All other voltage settings, T_A = +50°C ± 50°C with internal reference (Note 5)		±1.1		ppm/°C
INL Error	INL	25V setting, T_A = +25°C			±600	μV
INL Error	INL	500mV setting, T_A = +25°C			±170	µV
INL Drift		25V setting, T_A = 25°C ± 50°C (Note 5)		±35		μV/°C
INL Drift		500mV setting, T_A = +50°C ± 50°C (Note 5)		±3.5		µV/°C
Input Voltage Noise	V_N	25V setting, ADC sample rate is 57.6ksps, ADC mode is Continuous		85		μV_RMS
Input Voltage Noise	V_N	500mV setting, ADC sample rate is 900sps, ADC mode is Continuous		4		µV_P-P
Input Common Mode Range		25V setting, guaranteed by CMRR (Note 7)	-6.25		+6.25	V
Input Common Mode Range		All other voltage settings, guaranteed by CMRR (Note 7)	-1.25		+1.25	V
Common Mode Rejection Ratio	CMRR	25V setting, V_CM = -6.25V to +6.25V	60			dB
		2.5V setting, V_CM = -1.25V to +1.25V	80
		All other voltage settings, V_CM = -1.25V to +1.25V	92
Supply Rejection Ratio	PSRR	DC, V_HVDD = +5V to +24V		100		dB
Supply Rejection Ratio	PSRR	DC, V_HVSS = -24V to -5V		100		dB
50/60Hz Normal Mode Rejection		DCHNL_RATE[3:0] = 0b0010, 0b0011, 0b0100, 0b0101	87			dB
50/60Hz Normal Mode Rejection		DCHNL_RATE[3:0] = 0b0000, 0b0001	75			dB
Input Current		(Note 5)			±20	nA
Settling Time		25V setting, V_IN changes from 0V to +21V or 0V to -21V, digital output reaches 1% of final value, ADC sample rate is 57.6ksps, ADC mode is Continuous		100		µs
Settling Time		500mV setting, V_IN changes from 0V to +420mV or 0V to -420mV, digital output reaches 1% of final value, ADC sample rate is 57.6ksps, ADC mode is Continuous		100		µs
AMPLIFIER INPUTS (HART_IN, FB)
Input Bias Voltage				±2.5		V
AUX INPUTS (AUX1, AUX2)
Headroom		From V_HVSS (Note 3)	2.5			V
Headroom		From V_HVDD (Note 3)	2.5			V
Input Voltage Range	V_IN	ADC linear range, single-ended (Note 3)		+0.1 to +2.4		V
Input Voltage Range	V_IN	ADC linear range, differential (Note 3)		-2.3 to +2.3		V
Offset Error	V_OFF	T_A = +25°C before calibration		±0.5	±2.5	mV
Offset Calibration Range		Single-ended		0 to 2.5		V
Offset Calibration Range		Differential		±2.5		V
Offset Calibration Resolution				0.3		µV
Offset Drift		T_A = +50°C ± 50°C with internal reference (Note 5)		±1		µV/°C
Gain Error		T_A = +25°C before calibration			±4	%
Gain Calibration Range				0 to 200		%
Gain Calibration Resolution				0.1		ppm
Gain Drift		T_A = +50°C ± 50°C, with internal reference (Note 5)		±1		ppm/°C
INL Error	INL	T_A = +25°C		±15	±60	µV
INL Drift		T_A = +50°C ± 50°C (Note 5)		±50		nV/°C
Input Voltage Noise	V_N	ADC sample rate is 57.6ksps, ADC mode is Continuous		8		µV_RMS
Supply Rejection Ratio	PSRR	DC, V_HVDD = +5V to +24V		100		dB
Supply Rejection Ratio	PSRR	DC, V_HVSS = -24V to -5V		100		dB
50/60Hz Normal Mode Rejection		DCHNL_RATE[3:0] = 0b0010, 0b0011, 0b0100, 0b0101	87			dB
50/60Hz Normal Mode Rejection		DCHNL_RATE[3:0] = 0b0000, 0b0001	75			dB
Input Current	I_IN	(Note 5)			±20	nA
Settling Time		V_IN changes from 0.1V to +2.4V, digital output reaches 1% of final value, ADC sample rate is 57.6ksps, ADC mode is Continuous		100		µs
DAC REFERENCE (REF_DAC)
REF_DAC Output Voltage	V_{REF_DAC}	Internal reference		2.5		V
Output Voltage Accuracy		Referred to V_{REF_DAC}, T_A = +25°C	-0.2		+0.2	%
Output Voltage Temperature Coefficient		T_A = -40°C to +125°C (Note 5)		5		ppm/°C
Line Regulation		2.7V ≤ V_AVDD ≤ 3.6V			50	µV/V
REF_DAC Bypass Capacitor				100		pF
REF_DAC_EXT Input Range		External reference		2.5		V
ADC REFERENCE (REF_ADC)
REF_ADC Output Voltage	V_{REF_ADC}	Internal reference		2.5		V
Output Voltage Accuracy		Referred to V_{REF_ADC}, T_A = +25°C	-0.2		+0.2	%
Output Voltage Temperature Coefficient		T_A = -40°C to +125°C (Note 5)		5		ppm/°C
Line Regulation		2.7V ≤ V_AVDD ≤ 3.6V			250	µV/V
REF_ADC Bypass Capacitor				4.7		μF
REF_ADC_EXT Input Range		External reference		2.5		V
DIGITAL INPUTS (CS, SCLK, SDI, RST, SYNC, CLK, LDAC, GPIO0 THROUGH GPIO5)
Input Logic Low Voltage	V_IL				0.3×V_DVDD	V
Input Logic High Voltage	V_IH		0.7×V_DVDD			V
Input Hysteresis	V_HYS			200		mV
Input Leakage Current	I_IN		-1		+1	µA
Input Capacitance	C_IN			10		pF
DIGITAL OUTPUTS (SDO, RDY, INT, GPIO0 THROUGH GPIO5)
Output Logic Low Voltage	V_OL	I_SINK = 4mA			0.4	V
Output Logic High Voltage	V_OH	I_SOURCE = 4mA, except INT	0.9×V_DVDD			V
Three-State Leakage Current			-10		+10	µA
Three-State Output Capacitance				10		pF
POWER SUPPLIES
Analog Supply Voltage	V_AVDD		2.7	3.3	3.6	V
Digital Supply Voltage	V_DVDD		2.7	3.3	3.6	V
Positive High Voltage Supply	V_HVDD		5		28	V
Negative High Voltage Supply	V_HVSS		-24		-5	V
High Voltage Supply	V_HV	V_HVDD - V_HVSS	10		48	V
Positive High Voltage Output Supply	V_HVDDO		5		28	V
Negative High Voltage Output Supply	V_HVSSO		-24		-5	V
High Voltage Output Supply	V_HVO	V_HVDDO - V_HVSSO	10		48	V
DVDD POR Threshold		Voltage rising		1.6		V
HVDD Undervoltage Threshold		Voltage rising		1.5		V
Analog Supply Quiescent Current	I_{AVDD_Q}	Analog output voltage mode		5.5		mA
		Analog output current mode		5.5
		Analog inputs AI1-AI6		5.2
		Analog inputs and output		8
Digital Supply Quiescent Current	I_DVDD_{_Q}	Analog output voltage mode		1.4		mA
		Analog output current mode		1.4
		Analog inputs AI1-AI6		2.4
		Analog inputs and output		2.4
High-Voltage Quiescent Current	I_{HV_Q}	Analog output voltage mode, no load current		2.3		mA
		Analog output current mode, no load current		3.3
		Analog inputs AI1-AI6, AI1-AI6 at AGND		2.8
		Analog inputs and output, AI1-AI6 at AGND, no load current		3.5
Total Quiescent Power	P_Q	Analog output voltage mode, no load current, V_HVDD = V_HVDDO = +15V, V_HVSS = V_HVSSO = -15V		90		mW
		Analog output current mode, no load current, V_HVDD = V_HVDDO = +15V, V_HVSS = V_HVSSO = -15V		120
		Analog inputs AI1-AI6, AI1-AI6 at AGND, V_HVDD = V_HVDDO = +15V, V_HVSS = V_HVSSO = -15V		110
		Analog inputs and output, AI1-AI6 at AGND, no load current, V_HVDD = V_HVDDO = +15V, V_HVSS = V_HVSSO = -15V		140
PROTECTION
Thermal Shutdown Threshold	T_SHDN	Temperature rising until the analog I/O configuration resets		+165		°C
Thermal Warning Threshold	T_WARN	Temperature rising until interrupt assertion		+145		°C
Thermal Warning Hysteresis	T_{WARN_HYS}			10		°C
TIMING CHARACTERISTICS
SCLK Frequency	f_SCLK	All SPI transactions except analog output DAC register read-back			20	MHz
SCLK Frequency	f_SCLK	Analog output DAC register read-back, registers 0x44 through 0x47			10	MHz
SCLK Clock Period	t_CP	All SPI transactions except analog output DAC register read-back	50			ns
SCLK Clock Period	t_CP	Analog output DAC register read-back, registers 0x44 through 0x47	100			ns
SCLK Pulse Width High	t_CH	All SPI transactions except analog output DAC register read-back	13			ns
SCLK Pulse Width High	t_CH	Analog output DAC register read-back for registers 0x44 through 0x47	40			ns
SCLK Pulse Width Low	t_CL	All SPI transactions except analog output DAC register read-back	20			ns
SCLK Pulse Width Low	t_CL	Analog output DAC register read-back, registers 0x44 through 0x47	40			ns
CS Fall Setup Time	t_CSS0	CS falling edge to first SCLK rising edge setup time	7			ns
CS Rise Setup Time	t_CSS1	CS rising edge to SCLK rising edge setup time	5			ns
CS Fall Hold Time	t_CSH0	SCLK rising edge to CS falling edge hold time	0			ns
CS Rise Hold Time	t_CSH1	SCLK falling edge to CS rising edge hold time	3			ns
CS Pulse Width High	t_CSW	Minimum CS pulse width high	150			ns
SDI Setup Time	t_DS	SDI setup time to SCLK rising edge	10			ns
SDI Hold Time	t_DH	SDI hold time after SCLK rising edge	5			ns
SDO Transition Time	t_DOT	SDO transition valid after SCLK falling edge			20	ns
SDO Hold Time	t_DOH	Output remains valid after falling edge of SCLK	1			ns
SDO Disable Time	t_DOD	CS rising edge to SDO disable, C_LOAD = 20pF			80	ns
ESD AND SURGE PROTECTION
ESD		Human Body Model, all pins		±1		kV
IEC Surge	V_SURGE	IEC 61000-4-5, 1.2/50μs pulse, pins AI1-AI6, 4.75kΩ series MELF resistor		±1		kV

Note 1:	Maximum and minimum limits are 100% tested with typical supply voltage levels at T_A = +25°C, unless otherwise noted. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and device characterization.
Note 2:	The output voltage is measured at the sense voltage input (AI3). The supply voltage must fulfill the input headroom requirements, as well as the output amplifier requirements. Assuming that AI1, AI2, and AI3 are connected to the output, AI1 dictates the headroom requirement. Assuming a 25mA load current, a ±12.5V output, and a 50Ω sense resistor, the minimum supply voltage to fulfill the AI1 headroom requirement is the output voltage (V_OUT) plus the voltage drop across the sense resistor plus 2.5V, resulting in a supply voltage requirement of ±16.25V. The minimum supply voltage required for the output amplifier is the sum of the V_OUT, the voltage across the sense resistor, the diode forward voltage, and the dropout voltage. For a 25mA load current, a ±12.5V output, a 50Ω sense resistor, and a diode forward voltage of 750mV, the minimum supply voltage required by the output amplifier is ±15.35V. Overall, the minimum supply voltage is ±16.25V.
Note 3:	Offset error, gain error, INL error, and settling times are only guaranteed in the linear range. The minimum and maximum specification of the linear range and input headroom are guaranteed through offset, gain, and INL error.
Note 4:	The threshold current specifies the typical current that triggers the short circuit protection. The average current that accounts for self heating of the device is significantly smaller due to the duty cycle when OVC_CTRL is set to logic low.
Note 5:	Not production tested. Guaranteed by design and device characterization.
Note 6:	The supply voltage must fulfill the AI1 and AI2 headroom requirements, as well as the output amplifier requirements. The minimum supply voltage required to fulfill the AI1 and AI2 headroom is 2.5V plus the output current times the sum of the load and cable resistances, and the voltage across the sense resistor. The minimum supply voltage required for the output amplifier is the output current times the sum of the load and cable resistances, the voltage across the sense resistor, the diode forward voltage, and the dropout voltage. For a 25mA output current, a load resistor of 500Ω, a cable resistance of 250Ω, a 50Ω sense resistor, and a diode forward voltage of 750mV, the minimum headroom for AI1 and AI2 requires a supply voltage of ±22.5V, while the supply voltage required by the output amplifier is ±21.6V. Overall, the minimum supply voltage is ±22.5V.
Note 7:	The maximum allowed input common-mode range depends on the signal amplitude. The minimum and maximum values given in the Electrical Characteristics table apply to the maximum signal amplitude allowed for a given setting. Refer to the PGA Input Common-Mode Range section for the allowed input common-mode range for smaller signal amplitudes.
Figure 1. SPI Write Timing (N=24 when CRC is Disabled, N=32 when CRC is Enabled)
Figure 2. SPI Read Timing (N = 24 when CRC is Disabled, N = 32 when CRC is Enabled)

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{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 2\u003c/strong\u003e","data-html":true,"data-content":"The output voltage is measured at the sense voltage input (AI3). The supply voltage must fulfill the input headroom requirements, as well as the output amplifier requirements. Assuming that AI1, AI2, and AI3 are connected to the output, AI1 dictates the headroom requirement. Assuming a 25mA load current, a ±12.5V output, and a 50Ω sense resistor, the minimum supply voltage to fulfill the AI1 headroom requirement is the output voltage (VOUT) plus the voltage drop across the sense resistor plus 2.5V, resulting in a supply voltage requirement of ±16.25V. The minimum supply voltage required for the output amplifier is the sum of the VOUT, the voltage across the sense resistor, the diode forward voltage, and the dropout voltage. For a 25mA load current, a ±12.5V output, a 50Ω sense resistor, and a diode forward voltage of 750mV, the minimum supply voltage required by the output amplifier is ±15.35V. Overall, the minimum supply voltage is ±16.25V."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 3\u003c/strong\u003e","data-html":true,"data-content":"Offset error, gain error, INL error, and settling times are only guaranteed in the linear range. The minimum and maximum specification of the linear range and input headroom are guaranteed through offset, gain, and INL error."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 4\u003c/strong\u003e","data-html":true,"data-content":"The threshold current specifies the typical current that triggers the short circuit protection. The average current that accounts for self heating of the device is significantly smaller due to the duty cycle when OVC_CTRL is set to logic low."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 5\u003c/strong\u003e","data-html":true,"data-content":"Not production tested. Guaranteed by design and device characterization."}

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{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 6\u003c/strong\u003e","data-html":true,"data-content":"The supply voltage must fulfill the AI1 and AI2 headroom requirements, as well as the output amplifier requirements. The minimum supply voltage required to fulfill the AI1 and AI2 headroom is 2.5V plus the output current times the sum of the load and cable resistances, and the voltage across the sense resistor. The minimum supply voltage required for the output amplifier is the output current times the sum of the load and cable resistances, the voltage across the sense resistor, the diode forward voltage, and the dropout voltage. For a 25mA output current, a load resistor of 500Ω, a cable resistance of 250Ω, a 50Ω sense resistor, and a diode forward voltage of 750mV, the minimum headroom for AI1 and AI2 requires a supply voltage of ±22.5V, while the supply voltage required by the output amplifier is ±21.6V. Overall, the minimum supply voltage is ±22.5V."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 7\u003c/strong\u003e","data-html":true,"data-content":"The maximum allowed input common-mode range depends on the signal amplitude. The minimum and maximum values given in the Electrical Characteristics table apply to the maximum signal amplitude allowed for a given setting. Refer to the PGA Input Common-Mode Range section for the allowed input common-mode range for smaller signal amplitudes."}