Detailed Description

The MAX22000 is an industrial-grade, software configurable analog input/output solution. The device offers one output that can be configured as voltage or current output, and also offers up to six analog inputs that can be configured as voltage or current inputs. Two of the analog inputs are configured as a differential programmable gain amplifier (PGA), allowing for both low- and high-voltage inputs. The other analog inputs are high-voltage single-ended inputs. The transmit path (analog output) and the receive path (analog inputs) are completely independent; thus, can be programmed for different configurations and modes of operation.

The MAX22000 provides a high-performance 18-bit DAC in the transmit path, and a 24-bit delta-sigma ADC in the receive path. A high-performance filter follows the ADC to provide 50Hz/60Hz normal mode rejection at select ADC data rates.

The device includes a high-performance 5ppm/°C (max) voltage reference on-chip. However, external references can optionally be used for either or both of the transmit and the receive path.

The MAX22000 provides five main modes of operation:

• Analog Output Voltage Mode (AOVM)
• Analog Output Current Mode (AOCM)
• Analog Input Voltage Mode (AIVM)
• Analog Input Current Mode (AICM)
• RTD and TC Modes

Mode selection using the GEN_CNFG register determines which of the available input ports, AI1 through AI6, are used. Analog input conversion on available ports is independent of analog output activity.

For example, providing an analog output voltage requires only the use of AI3 for voltage feedback. If the application only needs this mode, all the other input channels are available for other uses, including the use of AI1 and AI2 as a current sense amplifier (CSA). Providing an analog output current reserves both AI1 and AI2 for current feedback. In this case, the resistor across AI1 and AI2 should be 50Ω. AI1 and AI2 can also report current when providing an analog output voltage. Here, a 50Ω resistor results in a ±25mA current measurement range.

Current measurement using AI5 and AI6 of the MAX22000 relies on an external precision resistor to effect current-to-voltage conversion. For current measurements not using differential sense, a GPIO pin can control an external analog switch to connect or disconnect the current sense resistor electronically.

Alternatively, an application requiring all 4 main modes of operation leaves only AI4, AI5, and AI6 for general use.

Besides their use as general purpose analog inputs, AI5 and AI6 can also be configured as a differential programmable gain amplifier (PGA) for either low-voltage or high-voltage inputs.

Regardless of mode of operation, ports AUX1 and AUX2 are always available for cold junction measurements.

The MAX22000 implements a safety switch, activated by the LINE_CNFG bit in the GEN_CNFG register, ensuring a feedback path whether in a 2-wire, 3-wire, or 4-wire configuration.

To maintain the best accuracy, the MAX22000 provides multiple voltage and current ranges for its inputs and outputs.

Table 1 summarizes the available ranges. From narrowest to widest, the nominal range specifies the range for the intended application. The linear range encompasses the nominal range, where performance specifications such as gain error, offset error, INL, PSRR, and CMRR are still guaranteed. Even wider, the full-scale range defines the conversion limits of the data converters. This extended range guards against clipping of signals significantly beyond the nominal range of the application.

The MAX22000 sets the linear range at 105% of the nominal range, and the full-scale range at 125% of the nominal range. For example, for a ±10V nominal range, the MAX22000 provides a linear range of ±10.5V and a full-scale range of ±12.5V.

To provide other ranges, manage the codes in the digital domain. For example, for applications providing a ±5V range, limit the provided DAC code range between negative half-scale and positive half-scale, and double the received ADC code while using ±10V calibration coefficients.

If the signal amplitude into the PGA is known to be less than its selected full-scale range, the MAX22000 allows a greater input common-mode range than specified in the Electrical Characteristics tables.

For the 25V, 2.5V, 500mV, 250mV, and 125mV settings, the maximum allowed input common-mode range is calculated as follows:

where,

V_CM = Maximum input in common-mode range

V_REF = Reference voltage (2.5V)

V_PEAK = Peak input voltage

A = Gain constant as per Table 2

For the 12.5V input range, the maximum input common-mode range is:

Table 3 summarizes settling performance in AOVM and AOCM modes. Settling time is defined as the time for the output to reach 1% error in response to a step of 105% of the linear range.

AOVM 25V mode setting specifies bandwidth instead, using the load circuit shown in Figure 3.

The MAX22000 provides output short-circuit protection in AOVM mode, responding to possible output overcurrent conditions in one of two ways, selectable using the OVC_CTRL bit in the GEN_CNFG register. In automatic mode, the output goes high impedance when an overcurrent condition is detected, and retries for about 300µs every 6ms until the overcurrent condition ends.

Alternatively, in host controlled mode, the output goes high-impedance and resets bits AO_CNFG[3:0] to 0b0000. The output remains high-impedance until the user writes bits AO_CNFG[3:0] with a code for a proper output configuration.

Regardless of overcurrent mode, the OVC_INT interrupt bit (in the GEN_INT register) asserts high to indicate overcurrent detection. In automatic mode, the OVC_INT bit automatically deasserts low once the MAX22000 senses that the overcurrent condition ends.

The 300µs dwell time ensures that completely discharged capacitive loads up to 1µF, charging to ±10V do not falsely trigger an overcurrent condition in AOVM mode

An SPI interface allows communication of all important information between a system host and the MAX22000.

An optional CRC enhances confidence in the data communicated to and from the MAX22000. This feature, disabled by default after hardware reset or power-up (but not a software reset), can be enabled or disabled at any time through the SPI interface. When enabled, it affects both read and write SPI transactions.

All SPI transactions without CRC are 4 bytes long. When CRC is enabled, all SPI transactions become 5 bytes long.

For an SPI write transaction, the host appends a correct CRC, calculated from the 4 bytes of that SPI transaction. The MAX22000 checks the CRC and flags a CRC error should there be a mismatch.

During an SPI read transaction, the MAX22000 expects no CRC, so does not check for one. The MAX22000 appends a correct CRC, calculated from the first byte sent from the host (the address and R/W bit), followed by the 3 bytes of register content. It is up to the host to check the validity of this returned CRC.

SPI command format consists of a 7-bit register address, followed by a read/write bit, followed by 24 bits of data to read from or write to the register specified. The two possible SPI transaction formats are shown in Table 4 and Table 5.

When enabled, the CRC uses a polynomial based on 0x31 (x⁸ + x⁵ + x⁴ + x⁰). This CRC has the following properties:

• detects all errors involving an odd number of bits
• detects all double-bit errors
• detects an error burst of up to 8 bits
• calculates and checks the CRC based on the 32-bits that would have been sent were the CRC not enabled

Refer to AN27 for more details at: https://www.maximintegrated.com/en/app-notes/index.mvp/id/27.

CRC code parameters:

• Width = 8
• Polynomial = 0x31
• Input XOR = 0x00
• Output XOR = 0x00
• Input Reflected = True
• Output Reflected = True

CRC write example: To write 0x00_0F00 to register GEN_ CHNL_CTRL, the SPI  transaction from the host would be 0x06_000F_0011.

CRC read transaction example: To read the default value from register GEN_CNFG, the SPI transaction from the host would be 0x05_XXXX_XXXX. The returned value from the MAX22000 would be 0x05_1000_00CB.

The MAX22000 includes a 32-bit device tracking number, unique to each device manufactured, accessible through the SPI interface.

Besides tracking individual ICs, this feature can also enable tracking of individual products incorporating the MAX22000.

The analog output is driven by a high accuracy 18-bit, serial SPI input, digital-to-analog converter (DAC).

At power-up, the output is set to high-impedance. If subsequently programmed to switch to AOVM mode, the output goes to approximately 0V. If subsequently programmed to switch to AOCM mode, the output goes to approximately 0mA.

One of the settings, the +25V mode, is meant to support HART or to source power for a 4mA–20mA sensor. As described later, the MAX22000 supports either a signal from a HART modem through the HART_IN pin, or the DAC can generate HART modulation directly through the firmware.

To ease system calibration, the MAX22000 corrects DAC codes with an 18-bit gain and an 18-bit offset adjustment, as shown in Figure 4.

The DAC code written to AO_DATA_W (in the AO_DATA_ WR register) is a signed two's complement value. Thus, a code of 0x00000 results in a nominal zero voltage or current, a code of 0x20000 results in the most negative voltage or current, and a code of 0x1FFFF results in the most positive voltage or current output. Details about the code-to-output mapping can be seen in Table 6.

Though AO_DATA_W is always interpreted as a signed two's complement value, the 25V mode adds a fixed 25V offset to the analog output, effectively making it positive-only. In the 25V mode case, programmed voltages might be restricted due to HVDDO headroom restrictions.

The gain coefficient, AO_GAIN_W, is always an unsigned 18-bit binary code, representing a gain between 1 LSB, and one unity gain. Table 7 summarizes the gain correction range of the MAX22000, where the last columns specify the gain as shown in Figure 4.

The offset coefficient, AO_OFFSET_W, is always a signed two's complement 18-bit code, representing an offset between about positive half-scale and negative half-scale. Table 8 summarizes the offset correction range of the MAX22000.

The results of the correction calculations can saturate. Should the correction calculations result in overflow or underflow, the code clips to the appropriate level. For 25V AOVM, the saturation calculations are the same as with ±12.5V AOVM, with an additional 25V offset added after the output voltage is calculated.

Writing to any of the AO_DATA_WR, AO_GAIN_CORR_ WR, or AO_OFFSET_CORR_WR registers results in a recalculation of the corrected output code as shown in Figure 4, and updates the analog output once the calculations have completed.

The LDAC pin controls the latch between the corrected digital code and the DAC, and can help time analog output changes precisely.

If precise timing is not needed, the simplest approach would be to leave LDAC tied permanently low. Writing to AO_DATA_WR, AO_OFFSET_CORR_WR, or AO_ GAIN_CORR_WR starts a correction calculation. The MAX22000 provides a new output once these calculations complete. Likewise, transitioning LDAC from high to low after one of these registers is written, also provides a new output, even if LDAC transitions high again before correction calculations have completed.

For more precise timing control, keep LDAC high, and transition low after correction calculations have completed. The analog output updates coincide with this falling edge. To determine when the calculations have completed, either wait at least 2.5µs after completion of the SPI transaction writing one of the registers specified above, or poll the BUSY bit in the AO_STA_RD register waiting for it to read low.

Table 9 collects together in one place, the formulas mapping DAC data, gain, and offset codes to nominal output values. Recall that the calculation in brackets can saturate, so overflows and underflows limit to the maximum and minimum digital codes, respectively.

The MAX22000 limits digital gain correction to 1.0 or below. Commonly, applications need a small gain correction above or below unity. To allow for this, the MAX22000 output driver provides an analog gain of approximately 1.02, allowing for a small correction above 1.0 if needed.

As shown in Figure 5, connect both AGND_DAC pins together. Refer remote output loads to this system ground for best performance.

The MAX22000 supports HART devices in two ways. First, program a microcontroller to provide DAC samples, through the SPI interface, emulating the 1.2kHz and 2.2kHz sine waves characteristic of HART, following the correct format. Read ADC samples, also through the SPI interface, to demodulate the HART signal and recover the HART data. This technique requires no additional hardware, placing the burden of the HART interface implementation in the digital domain.

Alternatively, use an external HART modem. Couple the output of that modem to the MAX22000 HART_IN pin with a DC blocking network, as shown in Figure 6. Ensure that the high-pass cutoff frequency is approximately 100Hz or below.

In AOVM mode, the gain from the HART_IN pin to the output is five, so a 1V peak-to-peak input results in a 5V peak-to-peak output swing.

In AOCM mode, the transconductance, assuming a 50Ω current sense resistor, is 10mA/V, so a 1V peak-to-peak input results in a 10mA peak-to-peak output swing.

Due to analog output headroom requirements, HVDD and HVDDO must be at least 26.5V for the 24V output mode. Also, HVSS and HVSSO must be -5V or more negative.

A passive network between the output driver and the FB pin compensates for load variations.

Figure 7 shows a recommended compensation network offering stable performance over a wide range of resistive and capacitive loads in AOVM mode, and a wide range or resistive and inductive loads in AOCM mode.

The MAX22000 features a high-performance, 24-bit delta-sigma analog-to-digital (ADC) converter, achieving exceptional performance while consuming minimal power. This  ADC provides a selection of sample rates from 1sps up to 115.2ksps.

The delta-sigma modulator detects overrange conditions. The DOR bit in the DCHNL_STA register reports any such condition should it occur.

Post-conversion digital SINC filters provide better than 75dB 50Hz/60Hz normal mode rejection, and also provide overflow reporting. When an overflow occurs, the code returned is either 0x7FFFFF if positive overflow occurs, or 0x800000 if negative underflow occurs.

The MAX22000 also monitors the analog signals entering the ADC and reports an overrange condition in bit AOR in the DCHNL_STA register if the input to the ADC exceeds the full-scale range by approximately 120% or more. These conversions can result in nonsaturated digital codes, which might not meet the accuracy specifications in this data sheet.

An internal multiplexer (MUX), controlled through the AI_DCHNL_ SEL[3:0] bits in the GEN_CHNL_CTRL register, selects from 11 available sources. Both single-ended and differential sources are available through this MUX, as detailed in Table 13.

For most MUX selections, a minimum voltage results in a converted code of 0x800000, a zero voltage results in a converted code of 0x000000, and a maximum voltage results in a converted code of 0x7FFFFF.

The exception to this are the AUX1 and AUX2 inputs, where an input of zero volts results in a converted code of 0x800000, an input of +1.25V results in a converted code of 0x000000, and an input of +2.5V results in a converted code of 0x7FFFFF.

The DCHNL_MODE bits in the DCHNL_CMD register control whether ADC conversions occur. By default, at power-up, the ADC is in a standby power-down mode (0b01), performing no conversions and minimizing ADC power consumption.

Writing 0b01 to the DCHNL_MODE bits in the DCHNL_ CMD register powers down the MAX22000 ADC. If the DCHNL_PD bit of the DCHNL_CTRL1 register is set low, then the MAX22000 ADC enters a standby mode, where conversions stop, but the internal LDO and oscillator are still powered, enabling fast startup. If the DCHNL_PD bit is set high, the ADC is reset.

To convert data through the ADC, write 0b11 to the DCHNL_MODE bits. This triggers either a single conversion or starts a continuous series of conversions, depending on the state of the SCYCLE and CONTSC bits in the DCHNL_CTRL1 register.

Set the DCHNL_MODE bits to 0b01 before making any changes to the ADC settings, as well as gain and offset calibration coefficients.

Select the conversion mode based on conversion latency and MUX usage.

If focusing on a single source of analog data with fast transients, choose continuous conversion mode. Select this mode by setting the SCYCLE bit in the DCHNL_CTRL1 register low before starting conversions. It yields the highest conversion rates possible, up to 115.2ksps. In this mode, depending on the selected conversion rate, received data has an initial filter settling of 5 samples. Refer to Table 10 for a menu of conversion rates.

Similar to continuous conversion mode, continuous single-cycle mode provides an on-going stream of samples, but bypasses the filter settling delay. Select this mode by setting the SCYCLE bit high and the CONTSC bit also high (both in the DCHNL_ CTRL1 register). It provides continuous conversions with no added latency, bypassing the pipeline delay of continuous conversion mode. Refer to Table 11 for a menu of conversion rates.

To provide on-demand conversions, consider single-cycle mode, offering a single no-latency conversion, but otherwise similar to continuous single-cycle mode. Select this mode by setting the SCYCLE bit high and the CONTSC bit low. Refer to Table 12 for maximum possible data rates in this mode.

When in either continuous conversion mode or continuous single-cycle mode, halt the conversions by setting the DCHNL_MODE bits in the DCHNL_CMD register to 0b01. Changing the MUX selection to a different source (AI_DCHNL_SEL bits in the GEN_CHNL_CTRL register) also halts continuous conversions and switches the ADC to standby.

Table 10, Table 11, and Table 12 summarize the available sampling rates of the MAX22000. Use the appropriate table depending on the conversion mode selected. In each case, the left-most column of the table indicates what to write to the DCHNL_RATE bits of the DCHNL_CMD register. In all 3 tables, the sampling rates in bold represent those that provide more than 90dB of 50Hz/60Hz normal mode rejection.

To achieve the highest possible sampling rate in Table 10, 115.2ksps in continuous sampling mode, system calibrations must first be disabled by setting both the NOSYSG and the NOSYSO bits in the DCHNL_CTRL2 register to 1. If either of these bits are zero, the sampling rate is instead 57.6ksps. The RATE bits in the DCHNL_STA register do not reflect this.

The RDY pin indicates the availability of an ADC conversion result. A new conversion result always triggers a falling edge on RDY. A valid read of the DCHNL_DATA register causes a rising edge on RDY if it is low. In continuous conversion mode or continuous single-cycle mode, a new conversion result might become available before the previous one had been read. In this case, the MAX22000 transitions the RDY pin high approximately 0.5µs prior to indicating that new conversion result with a falling edge.

Existing conversion results remain available until about 0.5µs before the next conversion result. In continuous mode, RDY initially remains high for the first four conversion results, then goes low for the fifth result. See Figure 8 for more detailed RDY timing.

The SYNC pin—ideally in conjunction with an external clock—can be used to synchronize the data conversions to external events. Although the synchronization method also works with an internal clock, resynchronization is inevitable due to local oscillators with limited frequency accuracy. A highly stable external clock that can be shared by multiple MAX22000 devices, allows for much longer time intervals without the requirement of resynchronization.

Set bit SYNC_MODE in register DCHNL_CTRL2 to logic high to enable external synchronization mode. Optionally, set bit EXTCLK in register DCHNL_CTRL2 to logic high to use a highly accurate external clock signal.

The synchronization mode is used to detect if the current conversions are synchronized to a continuous pulse signal with a period greater than the data rate. The pulse width of the synchronization signal is not critical, as only the rising edge of the synchronization pulse is used as a timing reference. The pulse width, however, must be longer than 300ns if the internal clock source is used, and longer than twice the clock period if an external clock source is used. In addition, the low time of the SYNC signal between consecutive SYNC pulses must be longer than 300ns if the internal clock source is used, and longer than twice the clock period if an external clock source is used. Ideally, the frequency of the synchronization signal is an integer multiple of the conversion rate. The synchronization mode records the number of ADC clock cycles between a falling edge of RDY and the rising edge of the next SYNC pulse. At the following SYNC pulse, the number of ADC clock cycles between a falling edge of RDY and the rising edge of the SYNC pulse is evaluated again and compared to the recorded value. If the new number of ADC clock cycles differs by more than one from the recorded value, the conversion in progress is stopped, the digital filter content is reset, and a new conversion starts. As the digital filter is reset, the full digital filter latency is required before valid results are available. If the new ADC clock count is within the ±1 count limit, the conversions continue uninterrupted.

Figure 9 shows the timing relationship between the MAX22000 ADC clock and the SYNC signal. Due to startup delays, any SYNC pulses before the first falling edge of RDY are ignored. The first rising edge on the SYNC pin after a falling edge of RDY establishes the relationship between the SYNC signal and the conversion timing.

The MAX22000 can eliminate gain and offset errors of the entire analog input signal chain, including board-level components, as well as internal MAX22000 circuits. The MAX22000 stores unique calibration coefficients for each of the available input channels, as selected by the AI_DCHNL_SEL bits in the GEN_CHNL_CTRL register. This simplifies calibration, as the coefficients need only be loaded once after reset or power-up. The MAX22000 automatically uses the appropriate coefficients on-the-fly. The MAX22000 supports automatic gain and offset correction in hardware for all conversion modes except for continuous conversion at 115,200 samples per second. Before this two-point calibration can take effect, the user must:

• Select two voltages near the application’s full-scale maximum and minimum points for each selected channel used.
• Ensure that the calibration parameters for that channel are set to defaults.
• Apply these two voltages to the MAX22000, resulting in two codes.
• Calculate the gain and offset corrections for this channel.
• Format these for the MAX22000 gain and offset correction registers.
• Write these parameters to the appropriate registers, and repeat for any other channels being calibrated.

Select two test voltages near the application maximum and minimum. Supply them from a low noise source, and measure them with an accurate meter.

The MAX22000 employs indirect addressing to provide access to the offset and gain registers associated with each unique input channel. First, write the desired channel to the DCHNL_N_SEL register. Then, access calibration values with reads and writes to the DCHNL_N_SOC register for the offset, and the DCHNL_N_SGC for the gain.

The offset and gain values must be at their defaults when the test voltages are applied. The defaults are 0x000000 for the offset and 0xC00000 for the gain of 1.5. Also, the NOSYSG and the NOSYSO bits in the DCHNL_CTRL2 register must both be at their default 0.

As illustrated in Figure 11, apply two test voltages, perform a conversion on each, and record the returned codes. For V1 and V2, C1 and C2 are obtained.

Using the appropriate full-scale range voltage in Table 13, calculate the gain and offset as: 

Since 0xC00000 is a gain of 1.5 our measured gain should be near 1.5. Calculate GAIN x 2²³. Write the rounded value of this in the DCHNL_N_SGC register as an unsigned number. For example, A = 1.48 translates to 12,415,139 (BD70A3h) in register DCHNL_N_SGC.

OFFSET is in bits, and can be either positive or negative. Using the appropriate digital gain entry in Table 13, calculate OFFSET/(ADIG x 1.5). Write this value in the DCHNL_N_SOC register as a two’s complement number.

The MAX22000 now corrects all further data from this channel using these associated correction parameters.

The data channel conversions do not need to be stopped while accessing the offset and gain correction registers. The ADC can be running or stopped. The channel whose correction parameters are being accessed cannot be the same as the channel actively being converted. The data channel keeps converting with one exception. A write to the offset or gain correction registers for a channel currently being converted aborts that conversion. Additionally, if the ADC is in either continuous conversion mode or continuous single-cycle mode, all further conversions are halted as well.

Either offset correction, gain correction, or both can be disabled with the NOSYSG and NOSYSO bits in the DCHNL_CTRL2 register, but these bits are global, and would prohibit calibration for all channels if activated. If gain correction is disabled, the MAX22000 behaves as if  DCHNL_SGC is set to 0x800000. Note that this is 2/3 of the default gain correction value of 0xC00000. If offset correction is disabled, the MAX22000 behaves as if DCHNL_SOC is set to 0x000000.

A software reset puts the DCHNL_ prefix registers to their default state and resets internal state machines. It does not affect the DAC.

To effect an ADC software reset:

• Write 1 to the DCHNL_PD bit in the DCHNL_CTRL1 register.
• Write 0b01 to the DCHNL_MODE bits in the DCHNL_ CMD register.
• Poll the PDSTAT bits in the DCHNL_STA register until it reads 0b10.

The MAX22000 monitors its own temperature, and provides both a thermal warning and a protective thermal shutdown.

The THWRNG_INT bit is set in the GEN_INT register, should the die temperature reach approximately 145°C. This bit remains set until the die temperature drops below approximately 135°C, at which point this bit clears. This high temperature warning condition can be programmed to cause an interrupt assertion on the INT pin.

Should the die temperature exceed approximately 165°C, the THSHDN_INT bit in the GEN_INT register asserts high and the INT pin asserts low, indicating a high temperature shutown condition. Note that thermal shutdown is a non-maskable interrupt. The GEN_CNFG and GEN_ CHNL_CTRL registers are reset to their default state, except for the DAC_REF_SEL, the ADC_REF_SEL, and the CRC_EN bits.