Applications Information

The switching frequency (f_SW) for MAX20461 is programmable via the CONFIG1 resistor (on standalone variants) or by I²C register writes.

Higher switching frequencies allow for smaller PCB area designs with lower inductor values and less output capacitance. Consequently, peak currents and I²R losses are lower at higher switching frequencies, but core losses, gate charge currents, and switching losses increase.

To avoid AM band interference, operation between 500kHz and 1.8MHz is not recommended.

The input capacitor supplies the instantaneous current needs of the buck converter and reduces the peak currents drawn from the upstream power source. The input bypass capacitor is a determining factor in the input voltage ripple.

The input capacitor RMS current rating requirement (I_IN(RMS)) is defined by the following equation:

$I_{IN(RMS)} = I_{LOAD} \frac{ \sqrt{ V_{SENSP} \times (V_{SUPSW} - V_{SENSP}) } }{ V_{SUPSW} }$

I_IN(RMS) has a maximum value when the input voltage equals twice the output voltage ($V_{SUPSW} = 2 \cdot V_{SENSP}$), so I_IN(MAX) = $\frac{1}{2} \cdot$ I_LOAD(MAX). I_LOAD is the measured operating load current, while I_LOAD(MAX) refers to the maximum load current.

Choose an input capacitor that exhibits less than 10ºC self-heating temperature rise at the RMS input current for optimal long-term reliability.

The input voltage ripple is composed of V_Q (caused by the capacitor discharge) and V_ESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high ripple current capability at the input. Assume the contribution from the ESR and capacitor discharge is equal to 50%. Calculate the input capacitance and ESR required for a specified input voltage ripple using the following equations:

$ESR_{IN} = \frac{\Delta V_{ESR}}{I_{LOAD(MAX)} + \frac{\Delta I_{L}}{2}}$

where:

$\Delta I_{L} = \frac{ ( V_{SUPSW} - V_{SENSP} ) \times V_{SENSP} } { V_{SUPSW} \times f_{SW} \times L }$

and:

$C_{IN} = \frac { I_{LOAD(MAX)} \times D(1-D) } { \Delta V_{Q} \times f_{SW} }$ where $D = \frac{ V_{SENSP} } { V_{SUPSW} }$

Where D is the buck converter duty cycle.

Bypass SUPSW with 0.1μF parallel to 10μF of ceramic capacitance close to the SUPSW and PGND pins. The ceramic input capacitor of a buck converter has a high $\frac{di}{dt}$, minimize the PCB current-loop area to reduce EMI. Bypass SUPSW with 47μF of bulk electrolytic capacitance to dampen line transients.

Three key inductor parameters must be considered when selecting an inductor: inductance value (L), inductor saturation current (I_SAT), and DC resistance (R_DCR). To select the proper inductance value, the ratio of inductor peak-to-peak AC current to DC average current (LIR) must be selected. A small LIR will reduce the RMS current in the output capacitor and results in small output ripple voltage, but this requires a larger inductor. A good compromise between size and loss is LIR = 0.35 (35%). Determine the inductor value using the equation below,

$L = \frac {V_{SENSP} \times ( V_{SUPSW} - V_{SENSP}) } { V_{SUPSW} \times f_{SW} \times I_{LOAD(MAX)} \times LIR}$

where V_SUPSW and V_SENSP are typical values (such that efficiency is optimum for nominal operating conditions). Ensure the inductor I_SAT is above the buck converter's cycle-by-cycle peak current limit.

Proper PCB layout is critical for robust system performance. See the MAX20461 EV kit datasheet for a recommended layout. Minimize the current-loop area and the parasitics of the DC-DC conversion circuitry to reduce EMI. The input capacitor placement should be prioritized because in a buck converter, the ceramic input capacitor has high $\frac{di}{dt}$. Place the input capacitor, power inductor, and output capacitor as close as possible to the IC SUPSW and PGND pins. Shorter traces should be prioritized over wider traces.

A low-impedance ground connection between the input and output capacitor is required (route through the ground pour on the exposed pad). Connect the exposed pad to ground. Place multiple vias in the pad to connect to all other ground layers for proper heat dissipation. Failure to do so can result in the IC repeatedly reaching ther­mal shutdown. Do not use separate power and analog ground planes. Instead, use a single common ground and manage currents through component placement. High-frequency return current flows through the path of least impedance (through the ground pour directly underneath the corresponding traces).

USB traces must be routed as a 90Ω differential pair with an appropriate keep-out area. Avoid routing USB traces near clocks and high-frequency switching nodes. The length of the routing should be minimized and avoid 90° turns, excessive vias, and RF stubs.

The nominal cable resistance (with tolerance) for both the USB power wire (BUS) and return GND should be determined from the cable manufacturer. In addition, be sure to include the resistance from any inline or PCB connectors. Determine the desired operating temperature range for the application, and consider the change in resistance over temperature.

A typical application presents a 200mΩ BUS resistance with a matching 200mΩ resistance in the ground path. In this application, the voltage drop at the far end of the captive cable is 800mV when the load current is 2A. This voltage drop requires the voltage-adjustment circuitry of the IC to increase the output voltage to comply with the USB and Apple specifications.

MAX20461 is compatible with both USB-compliant and non-compliant loads. A compliant USB device is not allowed to sink more than 30mA and must not present more than 10μF of capacitance when initially attached to the port. The device then begins its HVD+/HVD- connection and enumeration process. After completion of the connect process, the device can pull 100mA/150mA and must not present a capacitance greater than 10μF. This is considered the hot-inserted, USB-compliant load of 44Ω in parallel with 10μF.

For non-compliant USB loads, the ICs can also support both a hot insertion and soft-start into a USB load of 2Ω in parallel with 330μF.

The USB load current is monitored by an internal current-sense amplifier through the voltage created across R_SENSE. MAX20461 offers a digitally adjustable USB current-limit threshold. See SETUP_2 or Table 10 to select an appropriate register or resistor value for the desired current limit.

Some systems require the need to supply up to 160% of I_LOAD(MAX) for brief periods. It is possible to increase the MAX20461 current limit beyond 3.04A (min) by decreasing R_SENSE using this scaling factor:

R_SENSE = 33mΩ $\cdot \frac{3.04A}{1.6 \cdot I_{LOAD(MAX)}}$.

Figure 9 shows a DC model of the voltage-correction function of MAX20461. Without voltage adjustment (V_ADJ = 0, GAIN[4:0] = 0), the voltage seen by the device at the end of the cable will decrease linearly as load current increases. To compensate for this, the output voltage of the buck converter should increase linearly with load current. The slope of SENSP is called R_COMP such that $V_{ADJ} = R_{COMP} \cdot I_{LOAD}$ and $R_{COMP} = GAIN[4:0]$ $\cdot R_{LSB} \cdot \frac {R_{SENSE}} {33m\Omega}$ (see Figure 10). The R_COMP adjustment values available on MAX20461 are listed in the GAIN[4:0] register description and are based on a 33mΩ sense resistor.

For $V_{DUT} = V_{NO\_LOAD}; 0 \leq I_{LOAD}$, R_COMP must equal the sum of the system resistances. Calculate the minimum R_COMP for the system so that V_DUT stays constant:

 $R_{COMP\_SYS} = R_{LR} + R_{SENSE} + R_{PCB} + R_{CABLE\_VBUS} + R_{CABLE\_GND}$

Where R_{CABLE_VBUS} + R_{CABLE_GND} is the round-trip resistance of the USB cable (including the effect from the cable shield, if it conducts current), R_LR is the buck converter’s load regulation expressed in mΩ (51mΩ typ.), and R_PCB is the resistance of any additional V_BUS parasitics (the V_BUS FET, PCB trace, ferrites, and the USB connectors). Find the setting for GAIN[4:0] using the minimum R_COMP.

GAIN[4:0] = $ceiling( \frac{ R_{COMP\_SYS}} {R_{LSB}} \cdot \frac {33m\Omega}{R_{SENSE}} )$

The nominal DUT voltage can then be estimated at any load current by:

$V_{DUT} = V_{NO\_LOAD} + R_{LSB} \cdot GAIN[4:0] \cdot \frac {R_{SENSE}} {33m\Omega} \cdot I_{LOAD} - R_{COMP\_SYS} \cdot I_{LOAD}$

USB Hi-Speed mode requires careful PCB layout with 90Ω controlled differential impedance, with matched traces of equal length and with no stubs or test points. MAX20461 includes high-bandwidth USB data switches (>1GHz). This means data-line tuning is generally not required. However, all designs are recommended to include pads that would allow LC components to be mounted on the data lines so that tuning can easily be performed later, if necessary. Tuning components should be placed as close as possible to the IC data pins, on the same layer of the PCB as the IC. The proper configuration of the tuning components is shown in Figure 11. Figure 12 shows the reference eye diagram used in the test setup. Figure 13 shows the MAX20461 high-voltage eye diagram on the standard EVKIT with no tuning components. Tuning inductors should be high-Q wire-wound inductors. Contact Maxim’s application team for assistance with the tuning process for your specific application.

The high-voltage MAX20461 requires no external ESD protection. All Maxim devices incorporate ESD protection structures to protect against electrostatic discharges encountered during handling and assembly. While competing solutions can latch-up and require the power to be cycled after an ESD event, the MAX20461 continues to work without latch-up. When used with the configuration shown in the Typical Application Circuit, the MAX20461 is characterized for protection to the following limits:

• ±25kV ISO 10605 (330pF, 2kΩ) Air Gap
• ±8kV ISO 10605 (330pF, 2kΩ) Contact
• ±15kV IEC 61000-4-2 (150pF, 330Ω) Air Gap
• ±8kV IEC 61000-4-2 (150pF, 330Ω) Contact
• ±15kV ISO 10605 (330pF, 330Ω) Air Gap
• ±8kV ISO 10605 (330pF, 330Ω) Contact

Note: All application-level ESD testing is performed on the standard evaluation kit with 1m captive cable.

The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. MAX20461 helps users design equipment that meets Level 4 of IEC 61000-4-2. The main difference between tests done using the Human Body Model and IEC 61000-4-2 is a higher peak current in IEC 61000-4-2. Because the series resistance is lower in the IEC 61000-4-2 ESD test model Figure 15, the ESD withstand-voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 17 shows the current waveform for the 8kV, IEC 61000-4-2 Level 4 ESD Contact Discharge test. The Air Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized.