| Package Code | F173A3FY+6 |
| Outline Number | 21-100343 |
| Land Pattern Number | 90-100129 |
| THERMAL RESISTANCE, FOUR-LAYER EV KIT BOARD | |
| Junction to Ambient (θJA) | 29°C/W |
| Junction to Case (θJC) | 10.51°C/W |
| THERMAL RESISTANCE, FOUR-LAYER JEDEC BOARD | |
| Junction to Ambient (θJA) | 38.41°C/W |
| Junction to Case (θJC) | 10.35°C/W |
| Package Code | F153A3FY+2 |
| Outline Number | 21-100624 |
| Land Pattern Number | 90-100214 |
| THERMAL RESISTANCE, FOUR-LAYER EV KIT BOARD | |
| Junction to Ambient (θJA) | 31.5°C/W |
| Junction to Case (θJC) | 10.51°C/W |
| THERMAL RESISTANCE, FOUR-LAYER JEDEC BOARD | |
| Junction to Ambient (θJA) | 37.82°C/W |
| Junction to Case (θJC) | 10.06°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using both the four-layer EV kit as well as the method described in JEDEC specification JESD51-7. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX20404AFOE%2FVY%2B
data-opMAX20404AFOE%2FVY%2BT
data-opMAX20405AFOF%2FVY%2B
data-opMAX20405AFOF%2FVY%2BT
data-opMAX20406AFOE%2FVY%2B
data-opMAX20406AFOE%2FVY%2BT
data-opMAX20406AFOB%2FVY%2BT
data-opMAX20405AFOB%2FVY%2BT
data-opMAX20404AFOB%2FVY%2B
data-opMAX20406AFOA%2FVY%2B
data-opMAX20406AFOA%2FVY%2BT
data-opMAX20404AFOK%2FVY%2B
data-opMAX20404AFOK%2FVY%2BT
data-opMAX20405AFOA%2FVY%2B
data-opMAX20404AFOA%2FVY%2B
data-opMAX20404AFOA%2FVY%2BT
data-opMAX20405AFOA%2FVY%2BT
data-opMAX20404AFOJ%2FVY%2BT
data-opMAX20404AFOJ%2FVY%2B
data-opMAX20404AFOB%2FVY%2BT
data-opMAX20406AFOD%2FVY%2B
data-opMAX20404AFOD%2FVY%2B
data-opMAX20404AFOC%2FVY%2BT
data-opMAX20406AFOC%2FVY%2B
data-opMAX20406AFOD%2FVY%2BT
data-opMAX20406AFOB%2FVY%2B
data-opMAX20405AFOD%2FVY%2BT
data-opMAX20405AFOC%2FVY%2BT
data-opMAX20405AFOC%2FVY%2B
data-opMAX20404AFOD%2FVY%2BT
data-opMAX20405AFOD%2FVY%2B
data-opMAX20405AFOB%2FVY%2B
data-opMAX20406AFOC%2FVY%2BT
data-opMAX20404AFOC%2FVY%2B
High-voltage-compatible input for circuit activation. If this pin is low, the part is off.High-Side Driver Supply. Connect a 0.1μF capacitor between LX and BST for proper operation.IC Supply Input. Connect a 1μF or larger ceramic capacitor in parallel with a 4.7μF cap from SUP to PGND.Power Ground. Connect all PGND pins together.BUCK Switching Node. High impedance when part is off. Connect LX to the switched side of the appropriate inductor.Analog Ground1.8V Internal BIAS Supply. Connect a minimum of 2μF ceramic capacitor to PGND.Feedback Pin. Connect a resistor-divider from OUT to FB to GND for external adjustment of output voltage. Connect to BIAS for internal fixed voltages.Buck Regulator Output Voltage-Sense Input. Bypass OUT to PGND with a minimum capacitor as for appropriate paragraph.Internal Voltage Loop Error-Amplifier Output. Connect to VEA of the target for dual-phase operation. Leave unconnected for single-phase operation.Open-Drain Reset Output. External pull-up required.SYNC. If connected to GND, Skip-mode operation is enabled under light loads. If connected to BIAS, forced-PWM mode is enabled.180-Degree Out-of-Phase Clock Output for Multiphase Operation. Leave SYNCOUT open for single-phase operation.