Applications Information

Connect FB to BIAS for a fixed 5V or 3.3V output voltage. To set the output to other voltages between 0.8V and 10V, connect a resistor-divider from the output (OUT) to GND Figure 2. Select R_FB2 (FB to GND resistor) less than or equal to 100kΩ. Calculate R_FB1 (OUT to FB resistor) with the following equation:

Equation 1:

$R_{\mathrm{FB}1}=R_{\mathrm{FB}2}·\left(\frac{V_{\mathrm{OUT}}}{V_{\mathrm{FB}}}-1\right)$

where V_FB is the feedback regulation voltage. See the Electrical Characteristics table.

 

Table 1 provides components selection recommendations for each output range for the adjustable-output configuration. Recommendations can be further optimized for specific applications. The CFF values listed in Table 1 are recommended based on R_FB1 = 100kΩ. The CFF recommendation changes with the R_FB1 selection.

The MAX20404/MAX20405/MAX20406/MAX20406E come with dual-phase capability where each IC can be either configured as a controller or target. The SYNCOUT pin of the controller outputs a 180-degree out-of-phase clock when SYNC is tied high (FPWM mode). For low-I_Q mode, the SYNC pin of the controller should be pulled low (Skip mode). In this mode, there is no clock present on SYNCOUT pin of the controller, and the controller IC enters Skip mode. The internal circuit of the target IC remains ON during this time and actively looks for the SYNCOUT signal from the controller. Since the target IC is ON, the quiescent current is slightly higher, even though both of the ICs skip pulses.

To improve the light-load efficiency and further reduce the I_Q, the target EN should be pulled low. This disables the target and its internal circuits, further reducing the I_Q. Table 2 summarizes the truth table for low-I_Q operation.

For setting the output voltage to internal fixed voltage, order the same fixed V_OUT setting for both controller and target ICs and connect the FB pin to its respective BIAS. It is recommended NOT to connect the FB pins of the controller and target together.

For setting the output voltage to a value other than the available fixed V_OUT options, connect a resistor-divider between OUT, FB, and GND as shown in Figure 3. An identical but separate resistor-divider for controller and target is recommended.

Inductor design is a compromise between the size, efficiency, control-loop bandwidth, and stability of the converter. Insufficient inductance value would increase the inductor current ripple, causing higher conduction losses and higher output voltage ripple. Since the slope compensation is fixed internally for the MAX20404/MAX20405/MAX20406/MAX20406E, it might also cause current-mode-control instability to appear. A large inductor reduces the ripple, but increases the size and cost of the solution and slows the response. Table 3 provides optimized inductance values for each switching frequency. The nominal standard value selected should be within ±30% of the specified inductance.

The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The MAX20404/MAX20405/MAX20406/MAX20406E incorporate a symmetrical pinout that can be leveraged for better EMI performance. Connect two high-frequency 0603 or smaller capacitors on two SUP pins on either side of the package for good EMI performance. Connect a high-quality, 4.7μF (or larger) low-ESR ceramic capacitor on the SUP pin for low-input voltage ripple.

A bulk capacitor with higher ESR (such as an electrolytic capacitor) is normally required as well to lower the Q of the front-end circuit and provide the remaining capacitance needed to minimize input-voltage ripple. The input capacitor RMS current requirement (I_RMS) is defined by the following equation:

Equation 6:

$I_{\mathrm{RMS}}=I_{\mathrm{LOAD}(\mathrm{MAX})}·\left(\frac{\sqrt{V_{\mathrm{OUT}}·\left(V_{\mathrm{SUP}}-V_{\mathrm{OUT}}\right)}}{V_{\mathrm{SUP}}}\right)$

I_RMS has a maximum value when the input voltage equals twice the output voltage:

$V_{\mathrm{SUP}}=2\times V_{\mathrm{OUT}}$

Therefore:

$I_{\mathrm{RMS}}=\frac{I_{\mathrm{LOAD}(\mathrm{MAX})}}{2}$

Choose an input capacitor that exhibits less than +10°C self-heating temperature rise at the RMS input current for optimal long-term reliability. The input-voltage ripple consists of ΔV_Q (caused by the capacitor discharge) and ΔV_ESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high ripple-current capability at the input. Assume the contribution from the ESR and capacitor discharge equal to 50%. Calculate the input capacitance and ESR required for a specified input voltage ripple using the following equations:

Equation 7:

${\mathrm{ESR}}_{\mathrm{IN}}=\frac{∆V_{\mathrm{ESR}}}{I_{\mathrm{OUT}}+{\displaystyle \raisebox{1ex}{$∆I_L$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}}$

where:

$∆I_L=\frac{\left(V_{\mathrm{SUP}}-V_{\mathrm{OUT}}\right)·V_{\mathrm{OUT}}}{V_{\mathrm{SUP}}·f_{\mathrm{SW}}·L}$

and:

$C_{\mathrm{IN}}=\frac{I_{\mathrm{OUT}}·D(1-D)}{∆V_Q·f_{\mathrm{SW}}}$

$D=\frac{V_{\mathrm{OUT}}}{V_{\mathrm{SUP}}}$

where:

I_OUT = maximum output current

D = duty cycle

Output capacitance is selected to satisfy the output load-transient, output voltage ripple, and closed-loop stability requirements. During a load step, the output current changes almost instantaneously, whereas the inductor is slow to react. During this transition time, the load-charge requirements are supplied by the output capacitor, which causes an undershoot/overshoot in the output voltage. For a buck converter that is controlled by inductor current, as employed in the MAX20404/MAX20405/MAX20406/MAX20406E, output capacitance also affects the control-loop stability.

The output ripple is composed of ΔV_Q (caused by the capacitor discharge) and ΔV_ESR (caused by the ESR of the output capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic capacitors, the entire output ripple is contributed by ΔV_ESR. Use Equation 8 to calculate the ESR requirement and choose the capacitor accordingly. If using ceramic capacitors, assume the contribution to the output-ripple voltage from the ESR and the capacitor discharge to be equal. The following equations show the output capacitance and ESR requirement for a specified output-voltage ripple.

Equation 8:

$\mathrm{ESR}=\frac{∆V_{\mathrm{ESR}}}{∆I_{P-P}}$

$C_{\mathrm{OUT}}=\frac{∆I{}_{P-P}}{8·∆V_Q·f_{\mathrm{SW}}}$

where:

$∆I_{P-P}=\frac{\left(V_{\mathrm{IN}}-V_{\mathrm{OUT}}\right)·V_{\mathrm{OUT}}}{V_{\mathrm{IN}}·f_{\mathrm{SW}}·L}$

$V_{\mathrm{OUT\_RIPPLE}}=∆V_{\mathrm{ESR}}+∆V_Q$

ΔI_P-P is the peak-to-peak inductor current as calculated above, and f_SW is the converter’s switching frequency.

The output capacitor supplies the step-load current until the converter responds with a greater duty cycle. The resistive drop across the output capacitor's ESR and the capacitor discharge causes a voltage droop during a step load. Use a combination of low-ESR tantalum and ceramic capacitors for better transient-load and ripple/noise performance. Keep the maximum output-voltage deviations below the tolerable limits of the electronics being powered. When using a ceramic capacitor, assume an 80% and 20% contribution from the output-capacitance discharge and the ESR drop, respectively. Use the following equations to calculate the required ESR and capacitance value:

Equation 9:

$C_{\mathrm{OUT}}=\frac{∆I}{∆V·2\pi ·f_C}$

where ΔI is the load change, ΔV is the allowed voltage droop, and f_C is the loop crossover frequency, which can be assumed to be the lesser of f_SW/10 or 100kHz. Any calculations involving C_OUT should consider capacitance tolerance, temperature, and voltage derating. The values in Table 4 are actual capacitances after considering these factors.

For optimal phase margin, the recommended output capacitances are shown in Table 4. If a lower or higher output capacitance is required for the application, contact the factory for an optimized solution.

Careful PCB layout is critical to achieve low switching losses and clean, stable operation. Use a multilayer board whenever possible for better noise immunity and power dissipation. See Figure 4 and the following guidelines for good PCB layout:

1) Use the correct footprint for the IC and place as many copper planes as possible under the IC footprint to ensure efficient heat transfer.

2) Place the ceramic input-bypass capacitors, C_BP and C_IN, as close as possible to the SUP and PGND pins on both sides of the IC. Use low-impedance connections (no vias or other discontinuities) between the capacitors and IC pins. C_BP should be located closest to the IC and should have very good high-frequency performance (small package size and high capacitance). This will provide the best EMI rejection and minimize internal noise on the device, which can degrade performance.

3) Place the inductor (L), output capacitors (C_OUT), bootstrap capacitor (C_BST) and BIAS capacitor (C_BIAS) in such a way as to minimize the area enclosed by the current loops. Place the inductor (L) as close as possible to the IC LX pin and minimize the area of the LX node. Place the output capacitors (C_OUT) near the inductor so that the ground side of C_OUT is near the CIN ground connection to minimize the current-loop area. Place the BIAS capacitor (C_BIAS) next to the BIAS pin.

4) Place the bootstrap capacitor C_BST close to the IC and use short wide traces to minimize the loop area in order to minimize the parasitic inductance. Use the nearest layer for return trace (C_BST to LX) to minimize the inductance further. Refer to the layout in the EV kit for optimum design. High parasitic inductance can impact switching speed (increase switching losses) and cause high dv/dt noise.

5) Use a continuous copper GND plane on the layer next to the IC to shield the entire circuit. GND should also be poured around the entire circuit on the top side. Ensure that all heat-dissipating components have adequate connections to copper for cooling. Use multiple vias to interconnect GND planes/areas for low impedance and maximum heat dissipation. Place vias at the GND terminals of the IC and input/output/ bypass capacitors. Do not separate or isolate PGND and GND connections with separate planes or areas.

6) Place the feedback resistor-divider (if used) near the IC and route the feedback and OUT connections away from the inductor and LX node and other noisy signals.