Pin Specifications

Pin Configurations I2C-Controlled WLP
Single-Pin-Enabled WLP
I2C-Controlled FC2QFN
Single-Pin-Enabled FC2QFN
PIN NAME FUNCTION
I2C-Controlled WLP Single-Pin-Enabled WLP I2C-Controlled FC2QFN Single-Pin-Enabled FC2QFN
Pin Description
A1 A1 1 1 CAP Bypass Capacitor Connection for Internal Supply. Connect through 470nF of capacitance to GND.
A2, B2, C2 A2, B2, C2 12 12 GND Ground
A3, A4 A3, A4 10, 11 10, 11 IN Input Supply. Bypass to GND with effective capacitance equal to the minimum of 5µF and the value of the derating curve (Figure 7) for a bias voltage VIN placed as close to the device as possible.
B1 B1 2 2 FAST Fast Transient Response. When FAST is high, the quiescent current of MAX20343/MAX20344 increases in order to improve response time to a load step. When FAST is low, the quiescent current is decreased to save power. The function of B1 is determined by the factory configuration of the device. See FastRSEL in Table 3 for the specific configuration of each device.
B1 B1 2 2 RSEL Output Voltage Select. Connect a resistor from RSEL to GND based on the desired output voltage. See Figure 6. The function of B1 is determined by the factory configuration of the device. See FastRSEL in Table 3 for the specific configuration of each device.
B3, B4 B3, B4 9 9 LVLX Switching Node. Connect to HVLX through a 1μH inductor if BBstFETScale = 0 or a 2.2μH inductor if BBstFETScale = 1.
C1 3 SCL I2C Serial Clock Input. For I2C versions, note the BBstEn setting. If a version is disabled by default an externally supplied source must be used for the I2C interface to enable the output by I2C command.
C1 3 INGOOD Input Power Good. LOW indicates that the CAP pin voltage is forced to VOUT and the input voltage is below VIN_UVLO_F when VOUT ≥ 3.3V and the soft-start period is complete. Power capabilities might be limited. If CAP is forced to VIN, INGOOD does not function when VIN < VIN_UVLO_F. It is an open drain output and should be connected to an external logic supply using a pullup resistor.
C3, C4 C3, C4 8 8 HVLX Switching Node. Connect to LVLX through a 1μH inductor if BBstFETScale = 0 or a 2.2μH inductor if BBstFETScale = 1.
D1 4 SDA I2C Serial Data Input/Open-Drain Output. For I2C versions, note the BBstEn setting. If a version is disabled by default an externally supplied source must be used for the I2C interface to enable the output by I2C command.
D1 4 EN Enable. Active-high.
D2 5 INT Interrupt Output. Open-drain, connect through pullup resistor to system logic supply.
D2 5 PGOOD Power Good Output. Indicates when output is ready for use. It is an open drain output and should be connected to an external logic supply using a pullup resistor.
D3, D4 D3, D4 6, 7 6, 7 OUT Buck-Boost Output. If BBstFETScale = 0, bypass to GND with effective capacitance equal to twice the value of the derating curve (Figure 7) for a bias voltage VOUT, placed as close to the device as possible. If BBstFETScale = 1, bypass to GND with effective capacitance equal to the value of the derating curve (Figure 7) for a bias voltage VOUT, placed as close to the device as possible.