| Package Code | W161C2+1 |
| Outline Number | 21-100328 |
| Land Pattern Number | Refer to Application Note 1891 |
| THERMAL RESISTANCE, SINGLE-LAYER BOARD | |
| Junction-to-Ambient (θJA) | |
| Junction-to-Case Thermal Resistance (θJC) | |
| THERMAL RESISTANCE, FOUR-LAYER BOARD | |
| Junction-to-Ambient (θJA) | 57.93°C/W |
| Package Code | F122B2F+1 |
| Outline Number | 21-100331 |
| Land Pattern Number | 90-100130 |
| THERMAL RESISTANCE, SINGLE-LAYER BOARD | |
| Junction-to-Ambient (θJA) | |
| Junction-to-Case Thermal Resistance (θJC) | |
| THERMAL RESISTANCE, FOUR-LAYER BOARD | |
| Junction-to-Ambient (θJA) | 58.70°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 23.10°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX20343BEWE%2BT
data-opMAX20343BEWE%2B
data-opMAX20343JEWE%2BT
data-opMAX20344EAFC%2BT
data-opMAX20344EAFC%2B
data-opMAX20343JEWE%2B
data-opMAX20343EEWE%2B
data-opMAX20343EEWE%2BT
data-opMAX20343HEFC%2B
data-opMAX20343HEFC%2BT
data-opMAX20343FEWE%2B
data-opMAX20343FEWE%2BT
data-opMAX20343IEWE%2BT
data-opMAX20343IEWE%2B
data-opMAX20343GEWE%2B
data-opMAX20343GEWE%2BT
data-opMAX20343MEWE%2BT
data-opMAX20343MEWE%2B
Bypass Capacitor Connection for Internal Supply. Connect through 470nF of capacitance to GND.GroundInput Supply. Bypass to GND with effective capacitance equal to the minimum of 5µF and the value of the derating curve (Figure 7) for a bias voltage VIN placed as close to the device as possible.Fast Transient Response. When FAST is high, the quiescent current of MAX20343/MAX20344 increases in order to improve response time to a load step. When FAST is low, the quiescent current is decreased to save power. The function of B1 is determined by the factory configuration of the device. See FastRSEL in Table 3 for the specific configuration of each device.Output Voltage Select. Connect a resistor from RSEL to GND based on the desired output voltage. See Figure 6. The function of B1 is determined by the factory configuration of the device. See FastRSEL in Table 3 for the specific configuration of each device.Switching Node. Connect to HVLX through a 1μH inductor if BBstFETScale = 0 or a 2.2μH inductor if BBstFETScale = 1.I2C Serial Clock Input. For I2C versions, note the BBstEn setting. If a version is disabled by default an externally supplied source must be used for the I2C interface to enable the output by I2C command.Input Power Good. LOW indicates that the CAP pin voltage is forced to VOUT and the input voltage is below VIN_UVLO_F when VOUT ≥ 3.3V and the soft-start period is complete. Power capabilities might be limited. If CAP is forced to VIN, INGOOD does not function when VIN < VIN_UVLO_F. It is an open drain output and should be connected to an external logic supply using a pullup resistor.Switching Node. Connect to LVLX through a 1μH inductor if BBstFETScale = 0 or a 2.2μH inductor if BBstFETScale = 1.I2C Serial Data Input/Open-Drain Output. For I2C versions, note the BBstEn setting. If a version is disabled by default an externally supplied source must be used for the I2C interface to enable the output by I2C command.Enable. Active-high.Interrupt Output. Open-drain, connect through pullup resistor to system logic supply.Power Good Output. Indicates when output is ready for use. It is an open drain output and should be connected to an external logic supply using a pullup resistor.Buck-Boost Output. If BBstFETScale = 0, bypass to GND with effective capacitance equal to twice the value of the derating curve (Figure 7) for a bias voltage VOUT, placed as close to the device as possible. If BBstFETScale = 1, bypass to GND with effective capacitance equal to the value of the derating curve (Figure 7) for a bias voltage VOUT, placed as close to the device as possible.