| PARAMETER | SYMBOL | CONDITIONS | MIN | TYP | MAX | UNITS | |
|---|---|---|---|---|---|---|---|
| BUCK-BOOST | |||||||
| Input Voltage Range | VIN_START | Input voltage required for startup (Note 2) | 1.9 | 5.5 | V | ||
| Quiescent Supply Current | IQ | No load, VOUT = 5V, VIN = 3.7V | SwoFrcIN = 1, TA = +85°C (MAX20343) | 3.51 | 5 | µA | |
| SwoFrcIN = 1, TA = +125°C (MAX20344) | 12.5 | ||||||
| IQ_FAST | FAST = 1 | 35 | μA | ||||
| Shutdown Supply Current | ISHDN | I2C controlled | 0.3 | µA | |||
| Maximum Output Operative Power (Note 3) | PMAX | Integrator enabled, VIN > 2.7V, VOUT ≥ 3.2V | BBstFETScale = 0, L = 1µH, COUT = 8µF | 3.5 | W | ||
| BBstFETScale = 1, L = 2.2µH, COUT = 4µF | 1.75 | ||||||
| Integrator disabled, VIN > 3.2V (Note 4), VOUT ≥ 3.2V | BBstFETScale = 0, L = 1µH, COUT = 8µF, TA = +85°C (MAX20343) | 3.2 | |||||
| BBstFETScale = 0, L = 1µH, COUT = 8µF, TA = +125°C (MAX20344) | 2.9 | ||||||
| BBstFETScale = 1, L = 2.2µH, COUT = 4µF, TA = +85°C (MAX20343) | 1.75 | ||||||
| BBstFETScale = 1, L = 2.2µH, COUT = 4µF, TA = +125°C (MAX20344) | 1.6 | ||||||
| Output-Voltage Set Range | VOUT | 50mV step resolution | 2.5 | 5.5 | V | ||
| VIN < 2.1V, SwoFrcIN = 0 (see the Input Operating Voltage section) | 3.2 | 5.5 | |||||
| Average Output-Voltage Accuracy | ACC_OUT | IOUT = 1mA, COUT_EFF = 8µF | -2.4 | +2.4 | % | ||
| Line Regulation Error | VLINE_REG | -1 | +1 | %/V | |||
| Load Regulation Error | VLOAD_REG | Integrator enabled, VIN = 2.7V, VOUT = 3.3V, BBstFETScale = 0, POUT = 3.5W | -1 | % | |||
| Integrator disabled, VIN = 3.7V, VOUT = 5V, POUT = 1.5W, BBstFETScale = 1, COUT = 4µF, L = 2.2µH | -3.2 | ||||||
| Line Transient Response | VLINE_TRAN | VOUT = 3.4V, VIN from 3.4V to 2.9V, 1μs fall time, ILOAD = 750mA, BBstIntegEn = 1, SwoFrcIN = 0 | 0 | mV | |||
| Load Transient Response | VLOAD_TRAN | VOUT = 5V, VIN = 3.7V, ILOAD = 10µA to 700mA, BBstIntegEn = 1 | -150 | mV | |||
| Input Supply Current During Startup | IIN_STUP | VIN = 3.6V, VOUT = 5V, ILOAD = 0 | 1 |
mA/ COUT(µF) | |||
| Maximum Output Power During Startup (Note 3) | IPWR_MAX_STUP | BBstFETScale = 0 | 400 | 600 | mW | ||
| BBstFETScale = 1 | 200 | 300 | |||||
| Startup Time | tSTARTUP | Time from VOUT = 0V to final value | I2C controlled | 9.6 | ms | ||
| RSEL, BBstRampEn = 0 | 32 | ||||||
| PGOOD Threshold | VPGOOD | 84.7 | %VOUT | ||||
| PGOOD Threshold Hysteresis | VPGOOD_HYS | 2.25 | %VOUT | ||||
| Active Discharge Current | IACTD | 20 | mA | ||||
| Passive Discharge Resistance | RPSVD | 1.2 | kΩ | ||||
| Input UVLO Rising Threshold | VIN_UVLO_R | VIN rising | Soft-start active, SwoFrcIN = 1, or VOUT set below 3.3V | 1.836 | V | ||
| VOUT set higher than 3.3V, SwoFrcIN = 0, soft-start period complete | 2.185 | ||||||
| Input UVLO Falling Threshold | VIN_UVLO_F | VIN falling | Soft-start active, SwoFrcIN = 1, or VOUT set below 3.3V | 1.782 | V | ||
| VOUT set higher than 3.3V, SwoFrcIN = 0, soft-start period complete | 2.101 | ||||||
| Output UVLO Falling Threshold | VOUT_UVLO_F | VOUT falling | 1.873 | V | |||
| Output UVLO Rising Threshold | VOUT_UVLO_R | VOUT rising | 1.963 | V | |||
| DIGITAL | |||||||
|
SDA, EN, SCL, |
ILK_IO | TJ = +25°C | -1 | +1 | µA | ||
| SDA, EN, SCL, FAST Input Logic High | VIO_IH | 1.4 | V | ||||
| SDA, EN, SCL, FAST Input Logic Low | VIO_IL | 0.4 | V | ||||
|
SDA, |
VIO_OL | IOL = 4mA | 0.4 | V | |||
| SCL Clock Frequency | fSCL | MAX20343B/E/F/G/M, MAX20344E | 400 | 680 | kHz | ||
| All other versions | 680 | ||||||
| Bus Free Time Between STOP and START Condition | tBUF | 0.75 | µs | ||||
| START Condition (Repeated) Hold Time | tHD_STA | (Note 5) | 0.35 | µs | |||
| Low Period of SCL Clock | tLOW | 0.75 | µs | ||||
| High Period of SCL Clock | tHIGH | 0.35 | µs | ||||
| Setup Time for a Repeated START Condition | tSU_STA | 0.35 | µs | ||||
| Data Hold Time | tHD_DAT | (Note 6) | 0 | 0.53 | µs | ||
| Data Setup Time | tSU_DAT | 100 | ns | ||||
| Setup Time for STOP Condition | tSU_STO | 0.35 | µs | ||||
| Spike Pulse Widths Suppressed by Input Filter | tSP | 50 | ns | ||||
| Note 1: | All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. |
| Note 2: | Output power across the input operating voltage range is limited by input current. Refer to TOC03 for details on how the power limit changes with VIN. |
| Note 3: | The parameter is not production tested and values are generated through characterization only. |
| Note 4: | Operation down to 2.7V is supported with the integrator disabled, but stability is only guaranteed up to 1.75W output power. Beyond 1.75W, oscillations could occur unless output capacitance is increased. |
| Note 5: | fSCL must meet the minimum clock low time plus the rise/fall times. |
| Note 6: | The maximum tHD_DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal. |
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 1\u003c/strong\u003e","data-html":true,"data-content":"All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 2\u003c/strong\u003e","data-html":true,"data-content":"Output power across the input operating voltage range is limited by input current. Refer to TOC03 for details on how the power limit changes with VIN."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 3\u003c/strong\u003e","data-html":true,"data-content":"The parameter is not production tested and values are generated through characterization only."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 4\u003c/strong\u003e","data-html":true,"data-content":"Operation down to 2.7V is supported with the integrator disabled, but stability is only guaranteed up to 1.75W output power. Beyond 1.75W, oscillations could occur unless output capacitance is increased."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 3\u003c/strong\u003e","data-html":true,"data-content":"The parameter is not production tested and values are generated through characterization only."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 5\u003c/strong\u003e","data-html":true,"data-content":"fSCL must meet the minimum clock low time plus the rise/fall times."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 6\u003c/strong\u003e","data-html":true,"data-content":"The maximum tHD_DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal."}