Applications Information

The MAX20343/MAX20344 is designed to be compatible with small case-size ceramic capacitors. As such, the device has low-input and low-output capacitance requirements to accommodate the steep voltage derating of 0603 and 0402 (imperial) capacitors. The sample derating curve for a 22µF nominal value capacitor in Figure 7 presents the minimum capacitance required at IN and OUT. To ensure stability and low noise, the capacitance value under bias on IN should be the minimum of 5µF and the value of Figure 7 at the lowest expected V_IN. The minimum capacitance value under bias on OUT should be equal to the value of Figure 7 at the lowest expected V_OUT for BBstFETScale = 1 and twice that value for BBstFETScale = 0. Note that the derating curve in Figure 7 is a sample only, refer to the manufacturer’s derating curve of the actual capacitor selected to ensure that the minimum capacitance values under bias are met.

Where BBstIPSet1 is the peak current setting described in register 0x03. When selecting an inductor, one primary factor in achieving high efficiency is the DCR of the inductor. For maximum efficiency, select an inductor with the lowest DCR possible in the required package size. Another factor to consider is magnetic losses. Generally magnetic losses are lower in inductors with larger physical size and/or higher saturation current ratings. In most cases ferrite inductors should be avoided as they tend to exhibit poor AC characteristics especially in discontinuous conduction mode (DCM).

When writing to the MAX20343/MAX20344 using I²C, the master sends a START condition (S) followed by the MAX20343/MAX20344 I²C write address. After the address, the master sends the register address of the register that is to be programmed. The master then ends communication by issuing a STOP condition (P) to relinquish control of the bus, or a REPEATED START condition (Sr) to communicate to another I²C slave. See Figure 8.

In this operation, the master sends an address and two data bytes to the slave device (Figure 9). The following procedure describes the single byte write operation:

• The master sends a START condition.
• The master sends the 7-bit slave address plus a write bit (low).
• The addressed slave asserts an ACK on the data line.
• The master sends the 8-bit register address.
• The slave asserts an ACK on the data line only if the address is valid (NACK if not).
• The master sends 8 data bits.
• The slave asserts an ACK on the data line.
• The master generates a STOP condition.

In this operation, the master sends an address and multiple data bytes to the slave device (Figure 10). The slave device automatically increments the register address after each data byte is sent, unless the register being accessed is 0x00, in which case the register address remains the same. The following procedure describes the burst write operation:

• The master sends a START condition.
• The master sends the 7-bit slave address plus a write bit (low).
• The addressed slave asserts an ACK on the data line.
• The master sends the 8-bit register address.
• The slave asserts an ACK on the data line only if the address is valid (NACK if not).
• The master sends 8 data bits.
• The slave asserts an ACK on the data line.
• Repeat 6 and 7 N-1 times.
• The master generates a STOP condition.

In this operation, the master sends an address plus two data bytes and receives one data byte from the slave device (Figure 11). The following procedure describes the single byte read operation:

• The master sends a START condition.
• The master sends the 7-bit slave address plus a write bit (low).
• The addressed slave asserts an ACK on the data line.
• The master sends the 8-bit register address.
• The slave asserts an ACK on the data line only if the address is valid (NACK if not).
• The master sends a REPEATED START condition.
• The master sends the 7-bit slave address plus a read bit (high).
• The addressed slave asserts an ACK on the data line.
• The slave sends 8 data bits.
• The master asserts a NACK on the data line.
• The master generates a STOP condition.

In this operation, the master sends an address plus two data bytes and receives multiple data bytes from the slave device (Figure 12). The following procedure describes the burst byte read operation:

• The master sends a START condition.
• The master sends the 7-bit slave address plus a write bit (low).
• The addressed slave asserts an ACK on the data line.
• The master sends the 8-bit register address.
• The slave asserts an ACK on the data line only if the address is valid (NACK if not).
• The master sends a REPEATED START condition.
• The master sends the 7-bit slave address plus a read bit (high).
• The slave asserts an ACK on the data line.
• The slave sends 8 data bits.
• The master asserts an ACK on the data line.
• Repeat 9 and 10 N-2 times.
• The slave sends the last 8 data bits.
• The master asserts a NACK on the data line.
• The master generates a STOP condition.

Data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX20343/MAX20344 generate ACK bits. To generate an ACK, pull SDA low before the rising edge of the ninth clock pulse and hold it low during the high period of the ninth clock pulse (Figure 13). To generate a NACK, leave SDA high before the rising edge of the ninth clock pulse and leave it high for the duration of the ninth clock pulse. Monitoring for NACK bits allows for detection of unsuccessful data transfers.

The following tables provide the device and register bit default values for the various available parts.