Detailed Description

The MAX20069B is highly integrated TFT power supply and LED backlight driver IC for automotive TFT-LCD applications. The IC integrates one buck-boost converter, one boost converter, two gate-driver supplies, and a boost/SEPIC converter that can power one to four strings of LEDs in the display backlight.

The source-driver power supplies consist of a synchronous boost converter and an inverting buck-boost converter that can generate voltages up to +15V and down to -7V. The positive source-driver can deliver up to 120mA, while the negative source driver is capable of 100mA. The positive source-driver-supply regulation voltage (V_POS) is set by connecting an external resistor-divider on FBP or through I²C. The negative source-driver-supply voltage (V_NEG) is always tightly regulated to -V_POS (down to a minimum of -7V). The source-driver supplies operate from an input voltage between 2.8V and 5.5V.

The gate-driver-power supplies consist of regulated charge pumps that generate up to +28V and -21.5V and can deliver up to 3mA each.

The IC features a quad-string LED driver that operates from a separate input voltage (BATT) and can power up to four strings of LEDs with 150mA (max) of current per string. The IC features logic-controlled pulse-width modulation (PWM) dimming, with minimum pulse widths as low as 500ns with the option of phase shifting the LED strings with respect to each other. When phase shifting is enabled, each string is turned on at a different time, reducing the input and output ripple as well as audible noise. With phase shifting disabled, each current sink turns on at the same time and allows parallel connection of current sinks.

The startup and shutdown sequences for all power domains are controlled using one of the seven preset modes that are selectable through a resistor on SEQ. If the SEQ pin is connected to IN (I²C control), any sequence can be controlled using the individual regulator-enable bits. When a regulator other than HVINP is enabled, the HVINP boost is automatically enabled if not previously active. In this case, the second regulator is enabled when the soft-start of HVINP has completed.

The source-driver power supplies consist of a boost converter with output switch and an inverting buck-boost converter that generates up to +15V (max) and down to -7V (min), respectively, and can deliver up to 120mA on the positive regulator and -100mA on the negative regulator. The positive source-driver power supply’s regulation voltage (V_POS) can be set by the  resistor-divider on FBP or through the I²C interface.

The negative source-driver supply voltage (V_NEG) is automatically tightly regulated to -V_POS. V_NEG cannot be adjusted independently of V_POS. In I²C mode, V_POS (and V_NEG) is set by writing to the appropriate register. When HVINP is set to a voltage greater than 7V in I²C mode, the NEG converter should be disabled to avoid damage to the device. If the NEG output is not needed, the external components can be omitted and INN should be connected to IN; LXN should be left open and NEG should be connected to GND.

The IC has robust fault and overload protection. In stand-alone mode, if any of the DGVEE, NEG, POS, or DGVDD outputs fall to less than 80% (typ) of their intended regulation voltage for more than 50ms (typ), or if a short-circuit condition occurs on any output for any duration, then all outputs latch off (at the same time without any power-down sequence)  and a fault condition is set. In I²C mode, only the output at fault is automatically disabled.

In stand-alone mode, the fault condition is cleared when the EN pin or IN supply are cycled. In I²C mode, the fault condition is cleared when the EN bit of the affected rail is set to 0 or when the EN pin or the IN power supply is cycled.

Both sections (TFT and WLED) have thermal-fault detection; only the section causing the thermal overload is turned off.

Thermal faults are cleared when the die temperature drops by 15°C.

When a fault is detected, FLTB goes low in I²C mode, while in stand-alone mode the FLTB output pulses at a duty cycle that indicates the source of the fault.

The IC’s source-driver and gate-driver outputs (DGVEE, NEG, POS, and DGVDD) can be controlled by the resistor value on the SEQ pin (stand-alone mode), or by the I²C interface if SEQ is connected to IN (I²C mode). In I²C mode, the IC is turned on once one of the rails is activated by means of the appropriate I²C command, and the sequence is controlled by the I²C commands.

All outputs are brought up with soft-start control to limit the inrush current.

In stand-alone mode, toggling the EN pin from low to high initiates an adjustable preset power-up sequence (see Table 1). Toggling the EN pin from high to low initiates an adjustable preset power-down sequence. The EN pin has an internal deglitching filter of 7μs (typ).

Note: A glitch in the EN signal with a period less than 7μs is ignored by the internal enable circuitry. After all the TFT outputs have exceeded their power-good levels, the backlight block is turned on.

In the above table:

• t₁ = t₅ = 15ms
• t₂ = t₆ = 30ms
• t₃ = t₇ = 45ms
• t₄ = t₈ = 60ms

The IC also includes a high-efficiency high-brightness LED driver that integrates all the necessary features to implement a high-performance backlight driver to power LEDs in medium-to-large-sized displays for automotive as well as general applications. The IC provides load-dump voltage protection up to 52V in automotive applications and incorporates two major blocks: a DC-DC controller with peak current-mode control to implement a boost or a SEPIC-type switched-mode power supply and a 4-channel LED driver with 20mA to 150mA constant-current-sink capability per channel.

The IC features constant-frequency, peak current-mode control with programmable slope compensation to control the duty cycle of the PWM controller. The DC-DC converter implemented using the controller generates the required supply voltage for the LED strings from a wide input supply range. Connect LED strings from the DC-DC converter output to the 4-channel constant-current-sink drivers (OUT1–OUT4) to control the current through the LED strings. A single resistor connected from the ISET input to ground adjusts the forward current through all four LED strings. Fine adjustment can be made to the LED current using the I²C interface, even in stand-alone mode.

The IC features adaptive voltage control that adjusts the converter output voltage depending on the forward voltage of the LED strings. This feature minimizes the voltage drop across the constant-current-sink drivers and reduces power dissipation in the device. The backlight boost and current sinks are enabled when the complete sequence of the TFT bias section is completed.

The IC provides a very wide (10,000:1) PWM dimming range at 200Hz dimming frequency (with a dimming pulse as narrow as 500ns possible). The internal dimming signal is derived from the DIM signal or from the phase-shift dimming logic. Phase shifting of the LED strings can be disabled in I²C mode by writing to the psen bit in the enable (0x02) register.

Other advanced features include detection and string disconnect for open-LED strings, partially or fully shorted strings, and unused strings. Overvoltage protection clamps the converter output voltage to the programmed OVP threshold in the event of an open-LED condition.

The shorted-LED string threshold is programmable using the led_short_th[1:0] bits in the cnfg_gen (0x01 register (in stand-alone mode, the threshold is fixed at 7.8V).

In I²C mode, the FLTB signal asserts low to indicate open-LED, shorted-LED, and overtemperature conditions if they are not masked. In stand-alone mode, a fault in the backlight section causes FLTB to pulse at 25% duty cycle. Disable individual current-sink channels by connecting the corresponding OUT_ to LGND_ through a 12kΩ resistor (starting with OUT4). In this case, FLTB will not indicate an open-LED condition for the disabled channel. The IC also features overtemperature warning and protection that shuts down the controller if the die temperature exceeds +160°C.

The IC backlight boost is a constant-frequency, current-mode controller designed to drive the LEDs in a boost or SEPIC configuration. The IC features multiloop control to regulate the peak current in the inductor, as well as the voltage across the LED current sinks to minimize power dissipation.

The default switching frequency is 2.2MHz, but this can be reduced to 440kHz by setting the bl_swfreq bit in the cnfg_gen (0x01) register. Programmable slope compensation is used to avoid subharmonic oscillation that can occur at > 50% duty cycles in continuous-conduction mode.

The external nMOSFET is turned on at the beginning of every switching cycle. The inductor current ramps up linearly until turned off at the peak current level set by the feedback loop. The peak inductor current is sensed from the voltage across the current-sense resistor (R_CS) connected from the source of the external nMOSFET to PGND.

The IC features leading-edge blanking to suppress the external nMOSFET switching noise. A PWM comparator compares the current-sense voltage plus the slope-compensation signal with the output of the transconductance error amplifier. The controller turns off the external nMOSFET when the voltage at CS exceeds the error amplifier’s output voltage (at the COMP pin). This process repeats every switching cycle to achieve peak current-mode control.

In addition to the peak current-mode-control loop, the IC has two other feedback loops for control. The converter output voltage is sensed through the OVP input, which goes to the inverting input of the error amplifier.

The OVP gain (A_OVP) is defined as V_OUT/V_OVP, or (R17 + R16)/R16. The other feedback comes from the OUT_ current sinks. This loop controls the headroom of the current sinks to minimize total power dissipation, while still ensuring accurate LED current matching. Each current sink has a window comparator with a low threshold of 0.68V and a high threshold of 0.93V. These comparators drive logic that controls an up/down counter. The up/down counter is updated on every falling edge of the DIM input and drives an 8-bit digital-to-analog converter (DAC), which sets the reference to the error amplifier.

The error amplifier’s reference input is controlled with an 8-bit DAC. The DAC output is ramped up during startup to implement a soft-start function (see the Startup Sequence section). During normal operation, the DAC output range is limited to between 0.6V and 1.25V. The DAC LSB determines the minimum output-voltage step according to the following equation.

Equation 1:

$V_{\mathrm{STEP\_MIN}}=V_{\mathrm{DAC\_LSB}}\times A_{\mathrm{OVP}}$

where V_{STEP_MIN} is the minimum output-voltage step, V_{DAC_LSB} is 2.5mV (typ), and A_OVP is the OVP resistor-divider gain.

The IC offers phase shifting of the LED strings. To achieve this, the DIM signal is sampled internally by a 10MHz clock.

When phase shifting is enabled, the sampled DIM input is used to generate separate dimming signals for each LED string that is shifted in phase. The resolution with which the DIM signal is captured degrades at higher DIM input frequencies; therefore, dimming frequencies between 100Hz and 3kHz are recommended, although higher dimming frequencies are technically possible. The phase shift between strings is determined by the following equation.

Equation 2:

$\Theta =\frac{360}{n}$

where n is the total number of strings being used and θ is the phase shift in degrees. The order of the sequence is fixed, with OUT1 as the first in the sequence and OUT4 as the last. See Figure 2 for a timing diagram example with phase shifting enabled.

The phase-shifting feature is enabled or disabled with the psen bit. In stand-alone mode (no I²C), the psen bit in register 0x02 is set high by default (phase shifting enabled). When phase shifting is disabled, all strings turn on/off at the same time. If multiple current sinks are being connected in parallel to achieve greater than 150mA per string, phase shifting should be disabled.

If a fault is detected, resulting in a string being disabled during normal operation, the phase shifting does not adjust. For example, if all four strings are used, each string is 90 degrees out of phase. If the fourth string is disabled due to a fault, there will still be 90-degree phase difference between each string.

When disabling unused strings, disable the higher-numbered OUT_ current sinks first.

Assuming the BATT input is above its UVLO and the TFT has completed the startup sequence, the V_CC regulator begins to charge up its output capacitor. Once the V_CC regulator output rises above the V_CC UVLO threshold, the IC goes through its power-up checks, including unused string detection and OUT_ short-to-ground detection. To avoid possible damage, the converter does not start if any OUT_ is detected as shorted to ground.

Any current sinks detected as unused are disabled to prevent a false fault-flag assertion during normal operation. After these checks have been performed, the converter begins to operate and the output voltage begins to ramp up. The DAC reference to the error amplifier is stepped upwards until the OVP pin reaches 0.6V (or 1.1V in fast startup mode).

This stage duration is fixed at approximately 50ms (22ms in fast startup mode).

The second stage begins once the first stage is complete and the DIM input goes high. During stage 2, the output of the converter is adjusted until the minimum OUT_ voltage falls within the window comparator limits of 0.68V (typ) and 0.93V (typ). The output ramp is again controlled by the DAC, which provides the reference for the error amplifier. The DAC output is updated on each rising edge of the DIM input. If the DIM input is a 100% duty cycle (DIM = high), then the DAC output is updated once every 10ms.

The total soft-start time can be calculated using the following equation in slow startup mode.

Equation 3:

$t_{\mathrm{SS}}=50\mathrm{ms}+\frac{V_{\mathrm{LED}}+0.81-\left(0.6\times A_{\mathrm{OVP}}\right)}{f_{\mathrm{DIM}}\times 0.01\times A_{\mathrm{OVP}}}$

where t_SS is the total soft-start time, 50ms is the fixed stage 1 duration, V_LED is the total forward voltage of the LED strings, 0.81V is midpoint of the window comparator, A_OVP is the gain of the OVP resistor-divider, f_DIM is the dimming frequency (use 100Hz if the DIM input duty cycle is 100%), and 0.01V is the maximum voltage step per clock cycle of the DAC.

In fast startup mode (with ADD connected to IN or the wled_ss_time bit in the fault_masks1 (0x0B) register set to 1), the following equation should be used.

Equation 4:

$t_{\mathrm{SS}}=22\mathrm{ms}+\frac{1.1\times A_{\mathrm{OVP}}-(V_{\mathrm{LED}}+0.81)}{f_{\mathrm{DIM}}\times 0.01\times A_{\mathrm{OVP}}}$

On power-up, the IC detects and disconnects any unused current-sink channels before entering the DC-DC converter soft-start. Disable the unused current-sink channels by connecting the corresponding OUT_ to LGND_ through a 12kΩ resistor. This avoids asserting the FLTB output for the unused channels. After soft-start, the IC detects open strings and disconnects them from the internal minimum OUT_ voltage detector. This keeps the DC-DC converter output voltage within safe limits and maintains high efficiency.

If any LED string is open, the voltage at the open OUT_ goes to GND. The DC-DC converter output voltage then increases to the overvoltage-protection threshold (at which point the PWM controller is switched off, holding NDRV low) set by the voltage-divider network connected between the converter output, OVP input, and GND; at that point, any current-sink output with V_{OUT_} < 300mV (typ) is disconnected from the minimum-voltage detector. Select V_{OUT_OVP} (which will be the maximum voltage the boost converter can produce) according to the equation below.

Equation 5:

$V_{\mathrm{OUT\_OVP}}>1.1\times (V_{\mathrm{LED\_MAX}}+1)$

where V_{LED_MAX} is the maximum expected LED string voltage. V_{OUT_OVP} should also be chosen such that the voltage at the OUT_ pins does not exceed the absolute maximum rating.

The upper resistor in the OVP resistor-divider (R17) can be selected using the following formula.

Equation 6:

$R17=R16\times (\frac{V_{\mathrm{OUT\_OVP}}}{1.23}-1)$

where 1.23V is the typical OVP threshold. Ensure that the minimum voltage on the OVP pin is always greater than 0.6V to avoid the boost converter latching off due to undervoltage by checking the following.

Equation 7:

$(V_{\mathrm{LED\_MIN}}+0.6)\times \frac{R16}{R16+R17}>0.6V$

where V_{LED_MIN} is the worst-case minimum LED string voltage. If all strings are detected as open or unused the boost converter is disabled. In this condition the boost undervoltage detection is also disabled to avoid signalling an undervoltage fault. When this occurs the device is latched off.

When an open-LED condition occurs, FLTB is asserted low in I²C mode or switches at 25% in stand-alone mode.

For boost-circuit applications, the OVP resistor-divider always dissipates power from the battery, through the inductor and switching diode. If ultra-low shutdown current is needed in stand-alone mode, a general-purpose MOSFET can be added between the bottom OVP resistor and ground, with the EN of the device controlling the gate of the MOSFET. This additional MOSFET disconnects the OVP resistor-divider path when the device is disabled.

The IC checks for shorted LEDs at each rising edge of DIM. An LED short is detected at OUT_ if the OUT_ voltage is greater than the value programmed using the led_short_th bits in register 0x01 (or 7.8V in stand-alone mode). Once a short is detected on any of the strings, the LED strings with the short are disconnected and the FLTB output flag asserts (unless the fault is masked) until the device detects that the shorts are removed on any of the following rising edges of DIM. Short-LED detection is disabled in low-dimming mode. If the DIM input is connected high, short-LED detection is performed continuously.

Short-LED detection is also disabled in cases where all active OUT_ channels rise above 2.8V (typ). This can occur in a boost-converter application when the input voltage becomes higher than the total LED string voltage drop, such as during a battery load dump. During a load dump or other input voltage transient an erroneous shorted-LED fault may be indicated if one of the outputs exceeds the shorted-LED detection threshold before the others. This condition is most likely to occur when phase-shifting is enabled.

The IC features four identical constant-current sources used to drive multiple high-brightness LED strings. The current through each one of the four channels is adjustable between 20mA and 150mA using an external resistor (R_ISET) connected between ISET and GND.

Select R_ISET using the formula below.

Equation 8:

$R_{\mathrm{ISET}}=\frac{1500}{I_{\mathrm{OUT\_}}}$

where I_{OUT_} is the desired output current for each of the four channels. All four channels can be paralleled together for string currents exceeding 150mA. When I²C control is used, the current in the strings can be reduced in steps by writing to the diout (0x06) register. The resolution of this setting is 0.5% of the value set by the resistor on ISET.

The FLTB output pin is an active-low, open-drain output that can be used to signal various device faults (for operation in stand-alone mode (see the Stand-Alone Mode section). When the I²C interface is used, the FLTB output can flag any or all of the following conditions:

• Open fault on any of the OUT_ pins
• Shorted-LED fault on any of the OUT_ pins
• Any OUT_ shorted to GND
• LED boost converter undervoltage or overvoltage
• Undervoltage on HVINP, POS, NEG, DGVDD, or DGVEE
• Thermal warning on LED drive section
• Thermal shutdown on either LED drive or TFT bias section

The above conditions can be masked from causing FLTB to go low by using the corresponding mask bit in the bl_fault_masks (0x0A), fault_masks1 (0x0B), and fault_masks2 (0x0C) registers, if available.

In standalone mode the duty.cycle output on the FLTB pin indicates the type of fault according to the following scheme:

• FLTB continuously low: Thermal-shutdown fault
• 25% duty cycle on FLTB: Fault in LED section
• 50% duty cycle on FLTB: Faults in both LED and TFT sections
• 75% duty cycle on FLTB: Fault in TFT section

The MAX20069B IC features an I²C, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 1MHz. The master, typically a microcontroller, generates SCL and initiates data transfer on the bus.

The Slave ID of the MAX20069B depends on the connection of the ADD pin and the selected device version (see Table 2).

A master device communicates with the MAX20069B by transmitting the correct Slave ID followed by the register address and data word. Each transmit sequence is framed by a START (S) or Repeated START (Sr) condition, and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.

The IC's SDA line operates as both an input and an open-drain output. A pullup resistor greater than 500Ω is required on the SDA bus. In general, the resistor has to be selected as a function of bus capacitance such that the rise time on the bus is not greater than 120ns. The IC's SCL line operates as an input only. A pullup resistor greater than 500Ω is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. In general, for the SCL-line resistor selection, the same SDA recommendations apply. Series resistors in line with SDA and SCL are optional. The SCL and SDA inputs suppress noise spikes to assure proper device operation even on a noisy bus.

The I²C interface can be reset at any time by taking the EN pin low for at least 25μs. When a reset is performed the registers are reset to their initial values. Since all enable bits will be reset the device outputs will be turned off and a complete re-initialization will be needed.