Typical Application Schematic
Serial Clock Input for I2C Communication or Speed Selection for 1-Wire Communication. Input only. For I2C communication, connect to the clock terminal of the battery pack. Connect to CSN for standard speed 1-Wire communication. Connect to the REG3 pin for overdrive 1-Wire communication. SCL/OD has an internal pulldown (IPD) for sensing pack disconnection.
SCL/OD
SCL/OD
Serial Data Input/Output for Both 1-Wire and I2C Communication Modes. Open-drain output driver. Connect to the DATA terminal of the battery pack. SDA/DQ has an internal pulldown (IPD) for sensing pack disconnection.
SDA/DQ
SDA/DQ
ALRT*
ALRT*
Device Ground and Current Measurement Positive Sense Point. Kelvin connect to cell side of the sense resistor.
CSP
CSP
CELL3*
CELL3*
System Ground and Current Measurement Negative Sense Point. Kelvin connect to load side of the sense resistor.
CSN
CSN
CELL2*
CELL2*
Cell Voltage Sense 1. Used for cell balancing and voltage sensing.
CELL1
CELL1
TH1*
TH1*
TH2*
TH2*
PACK+
PACK+
PACK-
PACK-
Internal 3.4V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG3
REG3
Internal 1.8V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG2
REG2
MAX17320
MAX17320
N
N
Charge Pump Output and Bypass. Bypass CP to IN with a 0.47μF/25V ceramic capacitor.
CP
CP
Charge FET Gate Control. Enable/disable the high-side CHG N-FET by driving the gate between CP and IN. Connect a 0.1μF capacitor from Charge FET gate to source.
CHG
CHG
Discharge FET Gate Control. Enable/disable the high-side DIS N-FET by driving the gate between CP and PCKP.
DIS
DIS
Connect to Positive Terminal of Pack Connector Through 1kΩ
PCKP
PCKP
N
N
3 TERM FUSE*
3 TERM FUSE *
N
N
PFAIL*
PFAIL*
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.
IN
IN
AOLDO*
AOLDO*
Battery Voltage Sense of Top Cell in Series Stack. Used for cell balancing and voltage sensing.
BATTS
BATTS
Zero-Volt Charge Path. Recovery charge current is set by the resistor from the PCKP pin to the ZVC pin. Leave ZVC open if not used.
ZVC
ZVC
TH3*
TH3*
TH4*
TH4*
SECONDARY PROTECTOR*
SECONDARY PROTECTOR *
Ground Pin. Connect to ground. Do not share the ground trace with the CSP Kelvin-sense trace.
GND
GND
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
10Ω
10Ω
10kΩ
10kΩ
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
0.47µF
0.47µF
0.1µF
0.1µF
0.1µF
0.1µF
0.47µF
0.47µF
0.47µF
0.47µF
0.47µF
0.47µF
5mΩ
5mΩ
100Ω
100Ω
100Ω
100Ω
1kΩ
1kΩ
0.01µF
0.01µF
10kΩ
10kΩ
*OPTIONAL
*OPTIONAL
Typical 2S-4S Battery Pack and System Implementation
Serial Clock Input for I2C Communication or Speed Selection for 1-Wire Communication. Input only. For I2C communication, connect to the clock terminal of the battery pack. Connect to CSN for standard speed 1-Wire communication. Connect to the REG3 pin for overdrive 1-Wire communication. SCL/OD has an internal pulldown (IPD) for sensing pack disconnection.
SCL/OD
SCL/OD
Serial Data Input/Output for Both 1-Wire and I2C Communication Modes. Open-drain output driver. Connect to the DATA terminal of the battery pack. SDA/DQ has an internal pulldown (IPD) for sensing pack disconnection.
SDA/DQ
SDA/DQ
ALRT*
ALRT*
Device Ground and Current Measurement Positive Sense Point. Kelvin connect to cell side of the sense resistor.
CSP
CSP
CELL3*
CELL3*
System Ground and Current Measurement Negative Sense Point. Kelvin connect to load side of the sense resistor.
CSN
CSN
CELL2*
CELL2*
Cell Voltage Sense 1. Used for cell balancing and voltage sensing.
CELL1
CELL1
TH1*
TH1*
TH2*
TH2*
PACK+
PACK+
PACK-
PACK-
Internal 3.4V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG3
REG3
Internal 1.8V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG2
REG2
MAX17320
MAX17320
N
N
Charge Pump Output and Bypass. Bypass CP to IN with a 0.47μF/25V ceramic capacitor.
CP
CP
Charge FET Gate Control. Enable/disable the high-side CHG N-FET by driving the gate between CP and IN. Connect a 0.1μF capacitor from Charge FET gate to source.
CHG
CHG
Discharge FET Gate Control. Enable/disable the high-side DIS N-FET by driving the gate between CP and PCKP.
DIS
DIS
Connect to Positive Terminal of Pack Connector Through 1kΩ
PCKP
PCKP
N
N
3 TERM FUSE
3 TERM FUSE
N
N
Permanent Failure Indicator. Connect to a three terminal fuse to take action in case of primary FET failure detection. If not used, connect to GND with a 1kΩ resistor.
PFAIL
PFAIL
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.
IN
IN
AOLDO*
AOLDO*
Battery Voltage Sense of Top Cell in Series Stack. Used for cell balancing and voltage sensing.
BATTS
BATTS
Zero-Volt Charge Path. Recovery charge current is set by the resistor from the PCKP pin to the ZVC pin. Leave ZVC open if not used.
ZVC
ZVC
TH3*
TH3*
TH4*
TH4*
SECONDARY PROTECTOR
SECONDARY PROTECTOR
Ground Pin. Connect to ground. Do not share the ground trace with the CSP Kelvin-sense trace.
GND
GND
BATTERY
BATTERY
SYSTEM
SYSTEM
ALWAYS-ON LOADS RTC
ALWAYS-ON LOADS RTC
CHARGER
CHARGER
SYSTEM LOAD
SYSTEM LOAD
*OPTIONAL
*OPTIONAL
The IC measures voltage of the cells and balances the charge using internal FETs and the balancing resistors. It also measures current using a sense resistor that is accumulated to give a coulomb count and measures temperature using an on-chip sensor or up to 4 external thermistors, since the cells are likely to be located far away from the IC. The protector control drives a pair of high-side N-channel FETs. The IC also opens a three-terminal fuse for harsh faults that necessitate the battery to be permanently disabled for safety reasons. To power small loads like real-time clocks or housekeeping microcontrollers that need to be always on, the IC provides a regulated output that stays alive even when the protection FETs are opened. This output powers down only when the cells are severely depleted and, therefore, prevents any further drain for safety reasons.
Typical Application with a Fuse
Serial Clock Input for I2C Communication or Speed Selection for 1-Wire Communication. Input only. For I2C communication, connect to the clock terminal of the battery pack. Connect to CSN for standard speed 1-Wire communication. Connect to the REG3 pin for overdrive 1-Wire communication. SCL/OD has an internal pulldown (IPD) for sensing pack disconnection.
SCL/OD
SCL/OD
Serial Data Input/Output for Both 1-Wire and I2C Communication Modes. Open-drain output driver. Connect to the DATA terminal of the battery pack. SDA/DQ has an internal pulldown (IPD) for sensing pack disconnection.
SDA/DQ
SDA/DQ
ALRT*
ALRT*
Device Ground and Current Measurement Positive Sense Point. Kelvin connect to cell side of the sense resistor.
CSP
CSP
CELL3*
CELL3*
System Ground and Current Measurement Negative Sense Point. Kelvin connect to load side of the sense resistor.
CSN
CSN
CELL2*
CELL2*
Cell Voltage Sense 1. Used for cell balancing and voltage sensing.
CELL1
CELL1
TH1*
TH1*
TH2*
TH2*
PACK+
PACK+
PACK-
PACK-
Internal 3.4V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG3
REG3
Internal 1.8V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG2
REG2
MAX17320
MAX17320
N
N
Charge Pump Output and Bypass. Bypass CP to IN with a 0.47μF/25V ceramic capacitor.
CP
CP
Charge FET Gate Control. Enable/disable the high-side CHG N-FET by driving the gate between CP and IN. Connect a 0.1μF capacitor from Charge FET gate to source.
CHG
CHG
Discharge FET Gate Control. Enable/disable the high-side DIS N-FET by driving the gate between CP and PCKP.
DIS
DIS
Connect to Positive Terminal of Pack Connector Through 1kΩ
PCKP
PCKP
N
N
3 TERM FUSE
3 TERM FUSE
N
N
Permanent Failure Indicator. Connect to a three terminal fuse to take action in case of primary FET failure detection. If not used, connect to GND with a 1kΩ resistor.
PFAIL
PFAIL
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.
IN
IN
AOLDO*
AOLDO*
Battery Voltage Sense of Top Cell in Series Stack. Used for cell balancing and voltage sensing.
BATTS
BATTS
Zero-Volt Charge Path. Recovery charge current is set by the resistor from the PCKP pin to the ZVC pin. Leave ZVC open if not used.
ZVC
ZVC
TH3*
TH3*
TH4*
TH4*
SECONDARY PROTECTOR
SECONDARY PROTECTOR
Ground Pin. Connect to ground. Do not share the ground trace with the CSP Kelvin-sense trace.
GND
GND
*OPTIONAL
*OPTIONAL
The IC can permanently open a three-terminal fuse with the PFAIL pin when a permanent failure is detected. A secondary protector can also be included to open the three-terminal fuse.
Pushbutton Schematic
MAX17320
MAX17320
SYSTEM INTERFACE PMIC
SYSTEM INTERFACE PMIC
N
N
SYSTEM AP
SYSTEM AP
N
N
N
N
Charge FET Gate Control. Enable/disable the high-side CHG N-FET by driving the gate between CP and IN. Connect a 0.1μF capacitor from Charge FET gate to source.
CHG
CHG
Discharge FET Gate Control. Enable/disable the high-side DIS N-FET by driving the gate between CP and PCKP.
DIS
DIS
BATT
BATT
BUTTON
BUTTON
1.8V (VIO)
1.8V (VIO )
Programmable Alert Output
ALRT
ALRT
OPTIONAL PULLUP
OPTIONAL PULLUP
PUSHBUTTON
PUSHBUTTON
The IC and the system can share a pushbutton to wake up the system and the IC. The diode on the system interface PMIC blocks the pulldown when there is no supply. This prevents the wakeup for the IC when the system interface PMIC loses power in ship mode. The diode on the ALRT pin prevents the alert pulldown from triggering a button action on the PMIC. This prevents accidental shutdown in the event of an uncleared alert for > 10 seconds. The FET between the IC and the System AP blocks the System AP pulldown from triggering the wakeup when the AP does not have power. The FET acts as a level shifter and passes the pulldown alert signal in both directions when the 1.8V voltage is present.