| A2 |
1 |
IN |
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND. |
| A3 |
2 |
CP |
Charge Pump Output and Bypass. Bypass CP to IN with a 0.47μF/25V ceramic capacitor. |
| A4 |
3 |
CHG |
Charge FET Gate Control. Enable/disable the high-side CHG N-FET by driving the gate between CP and IN. Connect a 0.1μF capacitor from Charge FET gate to source. |
| A5 |
4 |
DIS |
Discharge FET Gate Control. Enable/disable the high-side DIS N-FET by driving the gate between CP and PCKP. |
| B5 |
5 |
ZVC |
Zero-Volt Charge Path. Recovery charge current is set by the resistor from the PCKP pin to the ZVC pin. Leave ZVC open if not used. |
| A6 |
6 |
PCKP |
Connect to Positive Terminal of Pack Connector Through 1kΩ
|
| C5 |
7 |
ALRT |
Programmable Alert Output
|
| B6 |
8 |
SCL/OD |
Serial Clock Input for I2C Communication or Speed Selection for 1-Wire Communication. Input only. For I2C communication, connect to the clock terminal of the battery pack. Connect to CSN for standard speed 1-Wire communication. Connect to the REG3 pin for overdrive 1-Wire communication. SCL/OD has an internal pulldown (IPD) for sensing pack disconnection. |
| C6 |
9 |
SDA/DQ |
Serial Data Input/Output for Both 1-Wire and I2C Communication Modes. Open-drain output driver. Connect to the DATA terminal of the battery pack. SDA/DQ has an internal pulldown (IPD) for sensing pack disconnection. |
| D6 |
10 |
TH1 |
Thermistor Input 1. Connect a 10k/100k thermistor from TH1 to GND. Leave disconnected or connect to GND if not used. |
| E6 |
11 |
PFAIL |
Permanent Failure Indicator. Connect to a three terminal fuse to take action in case of primary FET failure detection. If not used, connect to GND with a 1kΩ resistor. |
| D5 |
12 |
AOLDO |
Always-On LDO. Configurable as 3.4V or 1.8V. Bypass to GND with a 0.47µF/10V ceramic capacitor. Connect to GND with a 10kΩ resistor if not used. |
| E5 |
13 |
REG3 |
Internal 3.4V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor. |
| E4 |
14 |
CSN |
System Ground and Current Measurement Negative Sense Point. Kelvin connect to load side of the sense resistor. |
| E3 |
15 |
CSP |
Device Ground and Current Measurement Positive Sense Point. Kelvin connect to cell side of the sense resistor. |
| D2 |
16 |
TH2 |
Thermistor Input 2. Connect 10k/100k thermistor from TH2 to GND. Leave disconnected or connect to GND if not used. |
| E2 |
17 |
REG2 |
Internal 1.8V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor. |
| C2 |
18 |
TH3 |
Thermistor Input 3. Connect a 10k/100k thermistor from TH3 to GND. Leave disconnected or connect to GND if not used. |
| B2 |
19 |
TH4 |
Thermistor Input 4. Connect a 10k/100k thermistor from TH4 to GND. Leave disconnected or connect to GND if not used. |
| E1 |
20 |
GND |
Ground Pin. Connect to ground. Do not share the ground trace with the CSP Kelvin-sense trace. |
| D1 |
21 |
CELL1 |
Cell Voltage Sense 1. Used for cell balancing and voltage sensing. |
| C1 |
22 |
CELL2 |
Cell Voltage Sense 2. Used for cell balancing and voltage sensing. |
| B1 |
23 |
CELL3 |
Cell Voltage Sense 3. Used for cell balancing and voltage sensing. |
| A1 |
24 |
BATTS |
Battery Voltage Sense of Top Cell in Series Stack. Used for cell balancing and voltage sensing. |
| B3, B4, C3, C4, D3, D4 |
— |
NC |
No Connect. The NC pins are not internally connected and can be used for routing vias in certain cases. B3, C3, D3 can take a via from ZVC and ALRT. B4, C4, D4 can take a via from TH2, TH3, TH4 and AOLDO. Other placement of the vias under the NC pins could cause noise to couple to the IC. |
