Package Information

30 WLP

Package Code	W302O2+1
Outline Number	21-100381
Land Pattern Number	Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ_JA)	49°C/W
Junction to Case (θ_JC)	N/A

24 TQFN

Package Code	T2444+4C
Outline Number	21-0139
Land Pattern Number	90-0022
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ_JA)	68°C/W
Junction to Case (θ_JC)	11°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ_JA)	60°C/W
Junction to Case (θ_JC)	11°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

data-opMAX17320X12%2B

data-opMAX17320X20%2B

data-opMAX17320X22%2B

data-opMAX17320G20%2BT

data-opMAX17320G22%2BT

data-opMAX17320X20%2BT

data-opMAX17320X22%2BT

data-opMAX17320G10%2B

data-opMAX17320G10%2BT

data-opMAX17320G12%2B

data-opMAX17320G12%2BT

data-opMAX17320G20%2B

data-opMAX17320G22%2B

data-opMAX17320X10%2B

data-opMAX17320X10%2BT

data-opMAX17320X12%2BT

Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.Charge Pump Output and Bypass. Bypass CP to IN with a 0.47μF/25V ceramic capacitor.Charge FET Gate Control. Enable/disable the high-side CHG N-FET by driving the gate between CP and IN. Connect a 0.1μF capacitor from Charge FET gate to source.Discharge FET Gate Control. Enable/disable the high-side DIS N-FET by driving the gate between CP and PCKP.Zero-Volt Charge Path. Recovery charge current is set by the resistor from the PCKP pin to the ZVC pin. Leave ZVC open if not used.Connect to Positive Terminal of Pack Connector Through 1kΩProgrammable Alert OutputSerial Clock Input for I2C Communication or Speed Selection for 1-Wire Communication. Input only. For I2C communication, connect to the clock terminal of the battery pack. Connect to CSN for standard speed 1-Wire communication. Connect to the REG3 pin for overdrive 1-Wire communication. SCL/OD has an internal pulldown (IPD) for sensing pack disconnection.Serial Data Input/Output for Both 1-Wire and I2C Communication Modes. Open-drain output driver. Connect to the DATA terminal of the battery pack. SDA/DQ has an internal pulldown (IPD) for sensing pack disconnection.Thermistor Input 1. Connect a 10k/100k thermistor from TH1 to GND. Leave disconnected or connect to GND if not used.Permanent Failure Indicator. Connect to a three terminal fuse to take action in case of primary FET failure detection. If not used, connect to GND with a 1kΩ resistor.Always-On LDO. Configurable as 3.4V or 1.8V. Bypass to GND with a 0.47µF/10V ceramic capacitor. Connect to GND with a 10kΩ resistor if not used.Internal 3.4V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.System Ground and Current Measurement Negative Sense Point. Kelvin connect to load side of the sense resistor.Device Ground and Current Measurement Positive Sense Point. Kelvin connect to cell side of the sense resistor.Thermistor Input 2. Connect 10k/100k thermistor from TH2 to GND. Leave disconnected or connect to GND if not used.Internal 1.8V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.Thermistor Input 3. Connect a 10k/100k thermistor from TH3 to GND. Leave disconnected or connect to GND if not used.Thermistor Input 4. Connect a 10k/100k thermistor from TH4 to GND. Leave disconnected or connect to GND if not used.Ground Pin. Connect to ground. Do not share the ground trace with the CSP Kelvin-sense trace.Cell Voltage Sense 1. Used for cell balancing and voltage sensing.Cell Voltage Sense 2. Used for cell balancing and voltage sensing.Cell Voltage Sense 3. Used for cell balancing and voltage sensing.Battery Voltage Sense of Top Cell in Series Stack. Used for cell balancing and voltage sensing.No Connect. The NC pins are not internally connected and can be used for routing vias in certain cases. B3, C3, D3 can take a via from ZVC and ALRT. B4, C4, D4 can take a via from TH2, TH3, TH4 and AOLDO. Other placement of the vias under the NC pins could cause noise to couple to the IC.