Functional Diagram
Functional Diagrams
Block Diagram
MODELGAUGE M5 CORE
MODELGAUGE M5
CORE
Serial Clock Input for I2C Communication or Speed Selection for 1-Wire Communication. Input only. For I2C communication, connect to the clock terminal of the battery pack. Connect to CSN for standard speed 1-Wire communication. Connect to the REG3 pin for overdrive 1-Wire communication. SCL/OD has an internal pulldown (IPD) for sensing pack disconnection.
SCL/OD
SCL/OD
Serial Data Input/Output for Both 1-Wire and I2C Communication Modes. Open-drain output driver. Connect to the DATA terminal of the battery pack. SDA/DQ has an internal pulldown (IPD) for sensing pack disconnection.
SDA/DQ
SDA/DQ
ALRT
ALRT
Device Ground and Current Measurement Positive Sense Point. Kelvin connect to cell side of the sense resistor.
CSP
CSP
Cell Voltage Sense 3. Used for cell balancing and voltage sensing.
CELL3
CELL3
System Ground and Current Measurement Negative Sense Point. Kelvin connect to load side of the sense resistor.
CSN
CSN
Internal 3.4V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG3
REG3
Cell Voltage Sense 2. Used for cell balancing and voltage sensing.
CELL2
CELL2
Cell Voltage Sense 1. Used for cell balancing and voltage sensing.
CELL1
CELL1
Thermistor Input 1. Connect a 10k/100k thermistor from TH1 to GND. Leave disconnected or connect to GND if not used.
TH1
TH1
16-BIT ADC
16-BIT ADC
RBAL1
R
BAL
1
RBAL2
R
BAL
2
RBAL3
R
BAL
3
9Ω
9Ω
MUX
MUX
TH BIAS
TH BIAS
Thermistor Input 2. Connect 10k/100k thermistor from TH2 to GND. Leave disconnected or connect to GND if not used.
TH2
TH2
INTERNAL TEMPERATURE SENSOR
INTERNAL
TEMPERATURE
SENSOR
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
9Ω
9Ω
9Ω
9Ω
PACK+
PACK+
PACK-
PACK-
OPTIONAL THERMISTORS
OPTIONAL THERMISTORS
2-, 3-, OR 4-CELL OPERATION
2-, 3-, OR 4-CELL OPERATION
150Ω
150Ω
150Ω
150Ω
4.7V
4.7V
4.7V
4.7V
3.4V LDO
3.4V LDO
OUT
OUT
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.
IN
IN
1.8V LDO
1.8V LDO
0.47µF
0.47µF
Connect to Positive Terminal of Pack Connector Through 1kΩ
PCKP
PCKP
OUT
OUT
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.
IN
IN
Internal 1.8V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG2
REG2
0.47µF
0.47µF
I2C/1-WIRE INTERFACE
I
2
C
/1-WIRE
INTERFACE
MAX17320
MAX17320
RSENSE
R
SENSE
Internal 3.4V Regulator Output. Bypass to GND with a 0.47µF/10V ceramic capacitor.
REG3
REG3
CURRENT COMPARATORS
CURRENT
COMPARATORS
Always-On LDO. Configurable as 3.4V or 1.8V. Bypass to GND with a 0.47µF/10V ceramic capacitor. Connect to GND with a 10kΩ resistor if not used.
AOLDO
AOLDO
OUT
OUT
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.
IN
IN
0.47µF
0.47µF
Always-On LDO. Configurable as 3.4V or 1.8V. Bypass to GND with a 0.47µF/10V ceramic capacitor. Connect to GND with a 10kΩ resistor if not used.
AOLDO
AOLDO
3.4V OR 1.8V
3.4V OR 1.8V
OPTIONAL ALWAYS-ON SUPPLY
OPTIONAL
ALWAYS
-ON SUPPLY
0.1µF
0.1µF
0.1µF
0.1µF
RBAL4
R
BAL
4
Battery Voltage Sense of Top Cell in Series Stack. Used for cell balancing and voltage sensing.
BATTS
BATTS
9Ω
9Ω
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.
IN
IN
PUMP
PUMP
0.47µF
0.47µF
N
N
N
N
Charge Pump Output and Bypass. Bypass CP to IN with a 0.47μF/25V ceramic capacitor.
CP
CP
Charge FET Gate Control. Enable/disable the high-side CHG N-FET by driving the gate between CP and IN. Connect a 0.1μF capacitor from Charge FET gate to source.
CHG
CHG
Discharge FET Gate Control. Enable/disable the high-side DIS N-FET by driving the gate between CP and PCKP.
DIS
DIS
BATT
BATT
Charge Pump Output and Bypass. Bypass CP to IN with a 0.47μF/25V ceramic capacitor.
CP
CP
Connect to Positive Terminal of Pack Connector Through 1kΩ
PCKP
PCKP
10Ω
10Ω
PERMANENT FAILURE DETECTION
PERMANENT
FAILURE
DETECTION
Permanent Failure Indicator. Connect to a three terminal fuse to take action in case of primary FET failure detection. If not used, connect to GND with a 1kΩ resistor.
PFAIL
PFAIL
3 TERM FUSE
3 TERM
FUSE
N
N
1kΩ
1kΩ
CHARGE DETECT
CHARGE DETECT
Connect to Positive Terminal of Pack Connector Through 1kΩ
PCKP
PCKP
SHORT-CIRCUIT DETECT
SHORT-CIRCUIT DETECT
SHORT-CIRCUIT REMOVE
SHORT-CIRCUIT REMOVE
PCKP PULLDOWN (PKSINK)
PCKP PULLDOWN (PKSINK)
Ground Pin. Connect to ground. Do not share the ground trace with the CSP Kelvin-sense trace.
GND
GND
Thermistor Input 3. Connect a 10k/100k thermistor from TH3 to GND. Leave disconnected or connect to GND if not used.
TH3
TH3
Thermistor Input 4. Connect a 10k/100k thermistor from TH4 to GND. Leave disconnected or connect to GND if not used.
TH4
TH4
Zero-Volt Charge Path. Recovery charge current is set by the resistor from the PCKP pin to the ZVC pin. Leave ZVC open if not used.
ZVC
ZVC
RZVC
R
ZVC
ZVC PATH
ZVC PATH
10kΩ
10kΩ
Ground Pin. Connect to ground. Do not share the ground trace with the CSP Kelvin-sense trace.
GND
GND
Power Supply Input. Connect to the positive terminal of cell stack with a 10Ω resistor. Bypass with a 0.1µF/25V ceramic capacitor to GND.
IN
IN
SHORT FOR 2S
SHORT FOR 2S
SHORT FOR 2S OR 3S
SHORT FOR
2
S OR 3S
INCLUDE FOR 3S OR 4S
INCLUDE FOR
3
S OR 4S
INCLUDE FOR 4S
INCLUDE FOR
4
S
INTERNAL SELF-DISCHARGE DETECT
INTERNAL SELF-DISCHARGE DETECT
