| PARAMETER | SYMBOL | CONDITIONS | MIN | TYP | MAX | UNITS | |
|---|---|---|---|---|---|---|---|
| POWER SUPPLY | |||||||
| Supply Voltage | VIN | 4.2 | 18 | V | |||
| Shutdown Supply Current | IDD0 | Shutdown, VBATT = 18V, +25°C | 2.2 | 3.5 | μA | ||
| Ship Mode Supply Current | IDD1 | TA+50°C | 16 | 25 | μA | ||
| Active Supply Current | IDD2 | TA+50°C, average current, not including thermistor measurement current, AOLDO off | 38 | 57 | μA | ||
| REG3 Voltage | VREG3 | 3.4 | V | ||||
| REG2 Voltage | VREG2 | 1.8 | V | ||||
| Always-On LDO Voltage | VAOLDO | 1.8V output, ILOAD = 2mA | 1.62 | 1.8 | 1.98 | V | |
| 3.4V output, ILOAD = 2mA | 3 | 3.4 | 3.8 | ||||
| CHARGE PUMP | |||||||
| Charge Pump Output | VCP | 1.5 x IN < CPREG, VCP - IN | 1.5 x IN - 1 | 1.5 x IN | 1.5 x IN + 1 | V | |
| 6V selection | 5 | 6 | 7 | ||||
| 8V setting, VIN > 6V | 7 | 8 | 9 | ||||
| 10V setting, VIN > 7.5V | 9 | 10 | 11 | ||||
| CHG DRIVER | |||||||
| CHG Driver Output | VCHGHIGH | CHG is high, IN = 10V, 10MΩ resistor between CHG and IN | CP - 0.1 | CP | CP + 0.1 | V | |
| CHG Resistance | RCHGON | CHG is high | 4000 | Ω | |||
| RCHGOFF | CHG is low | 1000 | |||||
| DIS DRIVER | |||||||
| DIS Driver Output | VDISHIGH | DIS is high, IN = 10V, 10MΩ resistor between DIS and PCKP | CP - 0.1 | CP | CP + 0.1 | V | |
| DIS Resistance | RDISON | DIS is high | 4000 | Ω | |||
| RDISOFF | DIS is low | 1000 | |||||
| ZERO-VOLT RECOVERY | |||||||
| ZVC Minimum Voltage | VZVCMIN | IN = 0 | 10mA Recovery current | 1.4 | 2.4 | 3.3 | V |
| 30mA Recovery current | 2.1 | 2.9 | 3.8 | ||||
| 50mA Recovery current | 2.5 | 3.4 | 4.5 | ||||
| ANALOG-TO-DIGITAL CONVERSION | |||||||
| Cell Voltage Measurement Error | VGERR | TA = +25°C (Note 10) | -12.5 | +12.5 | mV | ||
| (Note 10) | -25 | +25 | |||||
| Cell Voltage Mismatch Error | VCMM | Cell voltage mismatch between channels (CELL1, 2, 3, 4) +25°C | -5 | +5 | mV | ||
| BATT Voltage Measurement Error | VBGERR | TA = +25°C, IN = BATTS, from 4.2V to 20V | -30 | +30 | mV | ||
| IN = BATTS, from 4.2V to 20V | -100 | +100 | |||||
| PCKP Voltage Measurement Error | VPGERR | TA = +25°C | -30 | +30 | mV | ||
| -100 | +100 | ||||||
| Cell Voltage Measurement Resolution | VLSB | Individual cell | 78.125 | μV | |||
| BATT Voltage Measurement Resolution | VBLSB | BATTS | 312.5 | μV | |||
| PCKP Voltage Measurement Resolution | VPLSB | PCKP pin | 312.5 | μV | |||
| Cell Voltage Measurement Range | VFS | (Note 10) | 2.1 | 4.9 | V | ||
| BATT Voltage Measurement Range | VBFS | BATTS pin | 4.2 | 19.6 | V | ||
| PCKP Voltage Measurement Range | VPFS | PCKP pin | 4.2 | 19.6 | V | ||
| Current Measurement Offset Error | IOERR | CSP = 0V, long-term average (Note 2) | ±2 | μV | |||
| Current Measurement Gain Error | IGERR | CSP between -50mV and +50mV | -1 | +1 | % of Reading | ||
| Current Measurement Resolution | ILSB | 1.5625 | μV | ||||
| Current Measurement Range | IFS | ±51.2 | mV | ||||
| Die Temperature Measurement Error | TIGERR | ±1 | ºC | ||||
| Die Temperature Measurement Resolution | TILSB | (Note 11) | 0.00391 | ºC | |||
| Thermistor Measurement Error | TEGERR | See the Thermistor Configuration section | ±1 | % of Reading | |||
| RESISTANCE AND LEAKAGE | |||||||
| Leakage Current, CELL1, CELL2, CELL3, BATTS, CSN, ALRT, PFAIL, ZVC, CHG, DIS | ILEAK | ALRT < 15V, IN < CP < 30V | -1 | +1 | μA | ||
| Cell-Balancing Resistance | RBAL | VBATT = 18V, IBAL = 50mA, between BATTS - CELL3, CELL3 - CELL2, CELL2 - CELL1, and CELL1 - CSP | 3 | 9 | 20 | Ω | |
| Communication Removal Test Current | IPD | SDA, SCL pin = 0.4V | 0.05 | 0.2 | 0.4 | μA | |
| INPUT / OUTPUT | |||||||
| Output Drive Low, ALRT, SDA/DQ, PFAIL | VOL | IOL = 4mA, REG3 = 3.4V | 0.4 | V | |||
| Output Drive High, PFAIL | VOH | IOH = -1mA | REG3-0.1 | V | |||
| Input Logic High, SCL/OD, SDA/DQ, ALRT | VIH | 1.5 | V | ||||
| Input Logic Low, SCL/OD, SDA/DQ, ALRT | VIL | 0.44 | V | ||||
| ALRT Wake Debounce | Sleep mode | 100 | ms | ||||
| COMPARATORS | |||||||
| Overcurrent Threshold Offset Error | OCOE | OC, OD, or SC comparator | -1.2 | +1.2 | mV | ||
| Overcurrent Threshold Gain Error | OCGE | OC, OD, or SC comparator | -5.0 | +5.0 | % of Threshold | ||
| NONVOLATILE MEMORY | |||||||
| Programming Supply Current | IPROG | Current from VBATT for block programming | 4 | 10 | mA | ||
| Block Programming Time | tBLOCK | 368 | 7360 | ms | |||
| Page Programming Time | tUPDATE | SHA secret update or learned parameters update | 64 | 1280 | ms | ||
| Nonvolatile Memory Recall Time | tRECALL | 5 | ms | ||||
| Write Capacity, Configuration Memory | nCONFIG | (Notes 2, 3, 4) | 7 | writes | |||
| Write Capacity, SHA Secret | nSECRET | (Notes 2, 3, 4) | 5 | writes | |||
| Write Capacity, Learned Parameters | nLEARNED | (Notes 2, 3, 4) | 99 | writes | |||
| Data Retention | tNV | (Note 2) | 10 | years | |||
| 1-WIRE INTERFACE, REGULAR SPEED | |||||||
| Time Slot | tSLOT | 60 | 120 | μs | |||
| Recovery Time | tREC | 1 | μs | ||||
| Write-0 Low Time | tLOW0 | 60 | 120 | μs | |||
| Write-1 Low Time | tLOW1 | 1 | 15 | μs | |||
| Read-Data Valid | tRDV | 15 | μs | ||||
| Reset-Time High | tRSTH | 480 | μs | ||||
| Reset-Time Low | tRSTL | 480 | 960 | μs | |||
| Presence-Detect High | tPDH | 15 | 60 | μs | |||
| Presence-Detect Low | tPDL | 60 | 240 | μs | |||
| 1-WIRE INTERFACE, OVERDRIVE SPEED | |||||||
| Time Slot | tSLOT | 6 | 16 | μs | |||
| Recovery Time | tREC | 1 | μs | ||||
| Write-0 Low Time | tLOW0 | 6 | 16 | μs | |||
| Write-1 Low Time | tLOW1 | 1 | 2 | μs | |||
| Read-Data Valid | tRDV | 2 | μs | ||||
| Reset-Time High | tRSTH | 48 | μs | ||||
| Reset-Time Low | tRSTL | 48 | 80 | μs | |||
| Presence-Detect High | tPDH | 2 | 6 | μs | |||
| Presence-Detect Low | tPDL | 8 | 24 | μs | |||
| 2-WIRE INTERFACE (I2C and SMBus) | |||||||
| SCL Clock Frequency | fSCL | (Note 5) | 400 | kHz | |||
| Bus Free Time Between a STOP and START Condition | tBUF | 1.3 | μs | ||||
| Hold Time (Repeated) START Condition | tHD:STA | (Note 6) | 0.6 | μs | |||
| Low Period of SCL Clock | tLOW | 1.3 | μs | ||||
| High Period of SCL Clock | tHIGH | 0.6 | μs | ||||
| Setup Time for a Repeated START Condition | tSU:STA | 0.6 | μs | ||||
| Data Hold Time | tHD:DAT | (Notes 7, 8) | 0 | 0.9 | μs | ||
| Data Setup Time | tSU:DAT | (Note 7) | 100 | ns | |||
| Rise Time of Both SDA and SCL Signals | tR | 5 | 300 | ns | |||
| Fall Time of Both SDA and SCL Signals | tF | 5 | 300 | ns | |||
| Setup Time for STOP Condition | tSU:STO | 0.6 | μs | ||||
| Spike Pulse Width Suppressed by Input Filter | tSP | (Note 9) | 50 | ns | |||
| Capacitive Load for Each Bus Line | CB | 400 | pF | ||||
| SCL, SDA Input Capacitance | CBIN | 6 | pF | ||||
| SCL Low Timeout | 30 | ms | |||||
| TIMING | |||||||
| Time-Base Accuracy | tERR | TA = +25°C | -1 | +1 | % | ||
| SHA Calculation Time | tSHA | 4.5 | 10 | ms | |||
| TH Precharge Time | tPRE | Time between turning on the TH bias and analog-to-digital conversions | 8.48 | ms | |||
| Power-on-Reset Time | tPOR | (Note 7) | 10 | ms | |||
| Task Period | tTP | 351.5 | ms | ||||
| Note 1: | All voltages are referenced to CSP. |
| Note 2: | Specification is Guaranteed by Design (GBD); not production tested. |
| Note 3: | Write capacity numbers shown have one write subtracted for the initial write performed during manufacturing test to set nonvolatile memory to a known value. |
| Note 4: | Due to the nature of one-time programmable memory, write endurance cannot be production tested. Follow the nonvolatile memory and SHA secret update procedures detailed in the data sheet. |
| Note 5: | Timing must be fast enough to prevent the IC from entering shutdown mode due to bus being low for a period greater than the shutdown timer setting. |
| Note 6: | fSCL must meet the minimum clock low time plus the rise/fall times. |
| Note 7: | The maximum tHD:DAT can only be met if the device does not stretch the low period (tLOW) of the SCL signal. |
| Note 8: | This device internally provides a hold time of at least 100ns for the SDA signal (referred to as the minimum VIH of the SCL signal) to bridge the undefined region of the falling edge of SCL. |
| Note 9: | Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. |
| Note 10: | BATTS to CELL3, CELL3 to CELL2, CELL2 to CELL1, or CELL1 to CSP, cell voltages between 2.3V and 4.9V; BATTS and CELL1 must be used. Neighbor CELL pins should be shorted if there is no battery connected between them. |
| Note 11: | Specification is for TH1/TH2/TH3/TH4 channels. |
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{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 10\u003c/strong\u003e","data-html":true,"data-content":"BATTS to CELL3, CELL3 to CELL2, CELL2 to CELL1, or CELL1 to CSP, cell voltages between 2.3V and 4.9V; BATTS and CELL1 must be used. Neighbor CELL pins should be shorted if there is no battery connected between them."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 10\u003c/strong\u003e","data-html":true,"data-content":"BATTS to CELL3, CELL3 to CELL2, CELL2 to CELL1, or CELL1 to CSP, cell voltages between 2.3V and 4.9V; BATTS and CELL1 must be used. Neighbor CELL pins should be shorted if there is no battery connected between them."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 2\u003c/strong\u003e","data-html":true,"data-content":"Specification is Guaranteed by Design (GBD); not production tested."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 11\u003c/strong\u003e","data-html":true,"data-content":"Specification is for TH1/TH2/TH3/TH4 channels."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 2\u003c/strong\u003e","data-html":true,"data-content":"Specification is Guaranteed by Design (GBD); not production tested."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 5\u003c/strong\u003e","data-html":true,"data-content":"Timing must be fast enough to prevent the IC from entering shutdown mode due to bus being low for a period greater than the shutdown timer setting."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 6\u003c/strong\u003e","data-html":true,"data-content":"fSCL must meet the minimum clock low time plus the rise/fall times."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 7\u003c/strong\u003e","data-html":true,"data-content":"The maximum tHD:DAT can only be met if the device does not stretch the low period (tLOW) of the SCL signal."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 9\u003c/strong\u003e","data-html":true,"data-content":"Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant."}
{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 7\u003c/strong\u003e","data-html":true,"data-content":"The maximum tHD:DAT can only be met if the device does not stretch the low period (tLOW) of the SCL signal."}