Applications Information

Applications Information IN Capacitor

Place at least a 1μF capacitor from the IN pin to GND to hold input voltage during any transients. If the upstream converter is too far away from the MAX15162, more input capacitors are recommended to be added to stabilize input voltage due to sudden load-current changes or MOSFET fast turn-off.

OUT Capacitor

The maximum capacitive load (C_MAX) that can be connected is a function of average startup current (I_INRUSH), the watchdog time (T_SU) and the input voltage (V_IN). C_MAXcan be calculated using the following relationship:

$C_{MAX} (μF) = \frac{I_{INRUSH} (mA) \times T_{SU} (ms)}{V_{IN} (V)}$

Equation 1: Maximum Output Capacitor

For example, for V_IN= 48V, T_SU= 250ms, and I_INRUSH= 28mA, C_MAXis 146µF.

Output capacitor values in excess of C_MAXcan result in a longer charging period and startup time, hence the possibility of watchdog timeout fault. Since the startup process is constant power limited, excessive capacitors will not cause more power dissipation or thermally stress the device.

Output Diode for Inductive Hard Short to Ground

In applications that require protection from a sudden short to ground with an inductive load or a long cable, a diode between the OUT terminal and ground is recommended. This is to prevent a negative spike on the OUT due to the inductive kickback during a short-circuit event.

Layout and Thermal Dissipation

To optimize the switch response time to turn off the output fast during short-circuit conditions, it is very important to keep all traces as short as possible to reduce the effect of undesirable parasitic inductance. Place the device close to the input supply to avoid too much parasitic inductance. Place input capacitors as close as possible to the device (no more than 5mm). Place output capacitors close to the load. If there are protection devices such as TVS, or diodes, they must be placed close to the part with short traces to reduce inductance. IN and OUT must be connected with wide short traces to the power bus.

To allow for the best cooling ability of the TQFN package, the EP (exposed pad) must be soldered directly to the board GND plane. It is highly recommended to apply four 20mil thermal vias on EP to help power dissipation, and reduce thermal resistance to the ambient. On the PCB board, the second layer from top and bottom should be continuous GND plane for electrical and thermal optimization. Place all support components close to connection pins. Connect the components to the GND with shortest trace length. The trace for IMON_ pin resistor R_IMON1/2 to the device must be as short as possible to reduce parasitic effects on the current limit and current reporting accuracy. Avoid any coupling of switching signals from the board to R_IMON traces.

Refer to the MAX15162 EV kit data sheet for a reference layout design.