Electrical Characteristics

Electrical Characteristics
(V_DD = +10V to +40V, V₅ = +4.5V to +5.5V, T_A = -40°C to +125°C, unless otherwise noted., Typical values are at T_A = +25ºC , V_DD = +24V, V_L= +3.3V and V₅= +5V, R_LIM = 50kΩ.) (Note 1)
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
V_DD SUPPLY
Supply Voltage	V_DD	Operting Conditions	10		40	V
Supply Voltage	V_DD	Tolerant	0		60	V
Supply Current	I_{DD_ON_HS}	HS mode, PP = low, IN = V_L, DOI high (no switching), no load, V₅ = V_L= REGIN = 5V, V_DD= 40V.		0.6	0.95	mA
	I_{DD_ON_PP}	PP mode, PP = high, 10kHz switching, V₅ = V_L= REGIN = 5V, V_DD = 40V, no load		0.85	1.4	mA
	I_{DD_ON_DI}	DI mode, DI_EN = V_L, REGIN = V_DD = 40V		0.13	0.3	mA
Undervoltage-Lockout Threshold	V_{DD_UVLO}	V_DD rising, V₅ = V_L	8.5	9.1	9.7	V
Undervoltage-Lockout Threshold	V_{DD_UVLO}	V_DD falling, V₅ = V_L	8	8.6	9	V
Undervoltage-Lockout Hysteresis	V_{DD_UVHYST}	V₅ = V_L		0.5		V
V_DD Overvoltage-Lockout Threshold	V_{DD_OVLO}	V_DD rising, V₅ = V_L	41.5	43.5	45	V
V_DD Overvoltage-Lockout Threshold	V_{DD_OVLO}	V_DD falling, V₅ = V_L	40.5	42.2	44	V
V_DD Overvoltage-Lockout Hysteresis	V_{DD_OVHYST}	V₅ = V_L		1		V
V_L LOGIC INTERFACE SUPPLY
V_L Supply Voltage	V_L		2.5		5.5	V
V_L Supply Current	I_L	All logic inputs high or low, all outputs unloaded		10	25	uA
V_L POR Threshold	V_{L_POR}	V_L falling	1.12	1.27	1.52	V
5V SUPPLY / LINEAR REGULATOR
REGIN Current HS Mode	I_{REGIN_ON_HS}	HS mode, REGIN = 40V, IN = V_L, no load on DOI, no load on V₅		0.3	0.5	mA
REGIN Current PP Mode	I_{REGIN_ON_PP}	PP = high, REGIN = 40V, 10kHz switching, no load on DOI, no load on V₅		0.35	0.6	mA
REGIN Current DI Mode	I_{REGIN_ON_DI}	DI_EN = V_L, REGIN = 40V			0.5	mA
V₅ Supply Current	I_{V5_HS}	HS mode, REGIN = V₅= 5V, IN = V_L, no load on DOI		0.24	0.4	mA
	I_{V5_PP}	PP mode, REGIN = V₅ = 5V, 10kHz switching, no load on DOI		0.3	0.5
	I_{V5_DI}	DI mode, DI_EN = high, REGIN = V₅= 5V		0.22	0.4
REGIN Undervoltage Threshold	V_{REG_UV}	REGIN rising. V₅ enabled when REGIN > V_{REG_UV}.	6.75		7.6	V
REGIN Undervoltage Hysteresis	V_REG_{_UVHYST}			0.45		V
V₅ Undervoltage-Lockout Threshold	V_{5_UVLO}	V₅ rising	3.8		4.2	V
V₅ Undervoltage-Lockout Hysteresis	V_{5UV_UVHYST}			0.3		V
V₅ Output Voltage	V₅	0mA - 20mA external load	4.75	5.0	5.25	V
V₅ Current Limit	I_{V5_CL}		25			mA
DRIVER OUTPUT (DOI)
HS On-Resistance	R_{DOI_ON_HS}	PP = X, IN = high, I_DOI= 500mA		120	240	mΩ
LS Output Low	V_{DOI_LOW}	PP = high, IN = low, I_DOI = 100mA			1.2	V
DOI Clamp Voltage	V_{DOI_}_CL	Relative to V_DD, I_DOI = 500mA, V_DD < V_{DD_OVLO}	-63	-55	-49	V
DOI Clamp Voltage	V_{DOI_CL}	Relative to GND, I_DOI = 500mA, V_{DD_OVLO} < V_DD < 60V	-4.5	-2.9	-1.5	V
DOI Leakage MAX14914, MAX14914A, MAX14914B	I_{DOI_LK}	V_DD = 40V, PP = IN = low, DI_EN = low, 0V < V_DOI < V_DD, V_L> V_{L_POR}	-60		60	μA
DOI Leakage MAX14914, MAX14914A, MAX14914B	I_{DOI_LK}	VDD = 60V, PP = IN = X, DI_EN = low, 0V < V_DOI < V_DD, V_L > V_{L_POR}	-150		150	μA
DOI Leakage MAX14914A	I_{DOI_LK}	V_DD = 40V, V_L < V_{L_POR}, PP = IN = DI_EN = X, 0V < V_DOI < 15V	-2.4		0	μA
		V_DD = 40V, V_L < V_{L_POR}, PP = IN = DI_EN = X, 0V < V_DOI < 15V, T = -40°C to +85°C	-0.4		0
		V_DD = 34V, V_L < V_{L_POR}, PP = IN = DI_EN = X, -15V < V_DOI < 0V		-80
OUTPUT DRIVER CURRENT LIMITING (DOI)
HS Current-Limit Minimum	I_{CLIM_HS_MIN}	R_LIM = 220kΩ	135	196	255	mA
HS Current-Limit Maximum	I_{CLIM_HS_MAX}	R_LIM = 27kΩ	1.3	1.6	1.9	A
HS Current-Limit Offset Error	I_{CLIM_HS_OE}	(Note 2)	-25		+25	mA
HS Current-Limit Gain Error	I_{CLIM_HS_GE}	(Note 2)	-20		+20	%
CLIM Voltage	V_CLIM			1.21		V
CLIM Short Resistor Threshold Value	R_{LIM_SHORT}	(Note 3)	10	12.9	15	kΩ
CLIM Open Resistor Threshold Value	R_{LIM_OPEN}	(Note 4)	440		750	kΩ
LS Current Limit	I_{CLIM_LS}		150		280	mA
DIGITAL INPUT / DOI MONITOR
DO Monitor Threshold Voltage	V_{TH_DO}	DI_EN = low, DOI rising	1.5		2.0	V
DO Monitor Threshold Voltage	V_{TH_DO}	DI_EN = low, DOI falling	1.3		1.8	V
DO Monitor Hysteresis	V_{HYS_DO}	DI_EN = low		0.2		V
DI Threshold Voltage	V_{TH_DI}	DI_EN = high, DOI rising	6.7		8	V
DI Threshold Voltage	V_{TH_DI}	DI_EN = high, DOI falling	5.5		6.8	V
DI Hysteresis	V_{HYS_DI}	DI_EN = high		1.2		V
DI Current Sink Type 1/3	I_DOI	DI_EN = high, PP = low, 0V < V_DOI < 5V			2.6	mA
DI Current Sink Type 1/3	I_DOI	DI_EN = high, PP = low, 8V < V_DOI < 40V, V_DOI < V_DD	2.0	2.3	2.6	mA
DI Current Sink Type 2	I_DOI	DI_EN = high, PP = high, 0V < V_DOI < 5V	0		7.5	mA
DI Current Sink Type 2	I_DOI	DI_EN = high, PP = high, 8V < V_DOI < 40V, V_DOI < V_DD	6.0	7.0	7.7	mA
LOGIC (I/O)
Input Voltage High	V_IH		0.7xV_L			V
Input Voltage Low	V_IL				0.3xV_L	V
Input Threshold Hysteresis	V_IHYST			0.11xV_L		V
Input Pulldown Resistor	R_I	All logic input pins	140	200	275	kΩ
Output Logic Low	V_OL	I_LOAD = +5mA			0.33	V
DOI_LVL Tristate Leakage	I_LEAK	GND < V_{DOI_LVL} < V_L	-1		+1	μA
FAULT Output Tristate Leakage	I_LEAK	GND < V_FAULT < V₅	-1		+1	µA
OV_VDD Leakage	I_LEAK	GND < V_{OV_VDD} < V_DD	-1		+1	μA
OV_CURR Leakage	I_LEAK	GND < V_{OV_CURR} < V_DD	-1		+1	μA
THERMAL PROTECTION
Driver Thermal-Shutdown Temperature	T_JSHDN	Junction temperature rising		170		°C
Driver Thermal-Shutdown Hysteresis	T_{JSHDN_HYST}			15		°C
Chip Thermal Shutdown	T_CSHDN	Temperature rising		150		°C
Chip Thermal-Shutdown Hysteresis	T_{CSHDN_HYST}			10		°C
TIMING CHARACTERISTICS / OUTPUT DRIVER (DOI)
Output Propagation Delay LH	t_{PD_LH}	PP = low, delay from IN to DOI rising by 1V, R_L= 5kΩ, C_L = 100pF (Figure 1)		0.4	1.5	µs
Output Propagation Delay HL	t_{PD_HL}	PP = low, delay between IN switching low to DOI falling by 1V, R_L= 5kΩ, C_L = 100pF, V_DD = 24V (Figure 1)		0.6	1.5	µs
Output Propagation Delay HL	t_{PD_HL}	PP = high, delay between IN switching low to DOI falling by 1V, R_L = 5kΩ, C_L = 100pF (Figure 1)		0.6	1.5	µs
DOI Output Rise Time	t_R	PP = X, 20% to 80% V_DD, R_L= 5kΩ, C_L = 100pF (Figure 2)		0.9	2	µs
DOI Output Fall Time	t_F	PP = low, 80% to 20% V_DD, V_DD= 24V, R_L= 5kΩ, CL = 100pF (Figure 2)		0.65	2	µs
DOI Output Fall Time	t_F	PP = low, 80% to 20% V_DD, V_DD = 24V, R_L = 47Ω, C_L = 100pF (Figure 2)		1		µs
TIMING CHARACTERISTICS / PROPAGATION DELAY (DOI to DOI_LVL)
Propagation Delay LH	t_{PDL_LH}	DI_EN = low, delay from DOI rising to 5V to DOI_LVL low (Figure 3)		2.7	5	µs
Propagation Delay LH DI	t_{PDL_HL_DI}	DI_EN = high, delay from DOI rising to 8V to DOI_LVL low		1.1		µs
Propagation Delay HL	t_{PDL_HL}	DI_EN = low, delay from DOI falling to 3.5V to DOI_LVL high		0.9	8	μs
Propagation Delay HL DI	t_{PDL_HL_DI}	DI_EN = high, delay from DOI falling to 5.5V to DOI_LVL high		0.9		μs
TIMING CHARACTERISTICS / GLITCH REJECTION (IN)
Pulse Length of Rejected Glitch	t_{FPL_GF}		0		80	ns
Glitch Filter Delay Time	t_{D_GF}			140	300	ns
TIMING CHARACTERISTICS / FAULT DETECTION (OV_VDD)
OV_VDD Threshold	V_{TH_OV_VDD}	DI_EN = low, relative to V_DD.MAX14914 and MAX14914A		0.22		V
OVLO_VDD Debounce Time	TD_{OVLO_VDD}	DI_EN = low. MAX14914 and MAX14914A.		200		μs

Electrical Characteristics—ESD and SURGE Protection
PARAMETER	SYMBOL	CONDITIONS	TYP	UNITS
ESD	V_ESD	DOI pin Contact Discharge (Note 5)	±7	kV
		DOI pin Air Discharge (Note 5)	±20
		All other pins. Human Body Model	±2
IEC Surge	V_SURGE	DOI to PGND or Earth GND per IEC 61000-4-5 (42Ω/0.5μF) (Note 6)	±2	kV

Note 1:	All the MAX14914ATE+ and MAX14914BATE+ units are production tested at T_A = +25°C. All the MAX14914AATE+ units are production tested at T_A = +25°C and +125°C. Specifications over temperature are guaranteed by characterization and design.
Note 2:	Specification is guaranteed by design; not production tested.
Note 3:	Lower resistor values than CLIM_SHORT act like a CLIM pin short to GND
Note 4:	Higher resistor values than CLIM_OPEN act like a CLIM open circuit.
Note 5:	Bypass V_DD pin to PGND with 1μF capacitor as close as possible to the device for high ESD protection.
Note 6:	With TVS protection on V_DD to PGND.
Figure 1. IN to DOI Propagation Delay
Figure 2. DOI Rise and Fall Time
Figure 3. DOI to DOI_LVL Propagation Delay

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DOI to DOI_LVL Propagation Delay\u003c/figcaption\u003e\n\u003c/figure\u003e\u003c/div\u003e","data-container":"body"}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 5\u003c/strong\u003e","data-html":true,"data-content":"Bypass VDD pin to PGND with 1μF capacitor as close as possible to the device for high ESD protection."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 6\u003c/strong\u003e","data-html":true,"data-content":"With TVS protection on VDD to PGND."}