Detailed Description

Detailed Description

The MAX11947 is an AISG v2.0 and v3.0-compliant, fully integrated modem with a 4:1 multiplexer facilitating connectivity between a single modem and up to four RF ports.

The MAX11947 receiver includes a narrow 200kHz bandwidth bandpass filter centered at the 2.176MHz carrier frequency. It also includes an OOK demodulator and a comparator that reconstructs the digital signal. The typical sensitivity threshold of the receiver is -15dBm (when set to the default value 0xB), in compliance with the AISG standard specifications. This threshold is adjustable through an internal register setting (RXSENS) from a -20.5dBm to -15dBm level.

The MAX11947 transmitter includes an OOK modulator, a bandpass filter that is compliant with the AISG spectral emission profile, and an output amplifier. The output power can be varied with an internal register setting (TXPWR) from under 0dBm to over +6dBm (measured at the MUX-selected RF port) to compensate for loss in the external circuitry and cabling. The OOK carrier is generated from an external crystal at 8.704MHz connected to the XTAL1 and XTAL2 pins. An external clock source at the same frequency can also be applied to XTAL1 from the SYNCOUT pin of another MAX11947.

The MAX11947 also features a DIR output to facilitate the RS-485 bus arbitration in tower-mounted equipment.

4:1 Multiplexer

The integrated 4:1 multiplexer allows the AISG system designer to connect a single modem to as many as four RF ports, simplifying implementation of a multi-primary or ALD PING-capable design. The MUX uses a CMOS analog switch architecture to provide a bidirectional signal, switchable between one common internal modem port and the four RF ports.

The 4:1 MUX provides both isolation and minimal crosstalk, allowing all four ports to be connected to a single modem without impacting the connected RF channels. To address the MUX performance, the port separation is characterized by three forms of isolation or crosstalk, which are primarily related to the frequencies involved: RF isolation, AISG isolation, and modem crosstalk.

Figure 2 shows a simplified block diagram of a single MUX RF port. A 50Ω series resistor is integrated into each RF port and the MUX common node is internally biased to approximately 1.5V DC.

Figure 2. MUX Port Diagram

The 4:1 MUX can be configured to either have all of the P_ RF ports internally terminated and the common node not connected, or any single P_ RF port can be connected to the MUX common node. All switch changes occur in a break-before-make sequence. When an RF port is not connected to the MUX common node, that P_ port is internally terminated through the 50Ω resistor to ground. When a port is selected, any previous selected port is terminated to GND prior to the new port connection being made. The process of connecting a P_ RF port to the common port is measured by the tSW time. This switching time is measured by monitoring the CSB and SCLK signals of the SPI interface and the DC level on the RF port. The time starts when the port change message is programmed into the RFPORT [1:0] bits in the MUX (0x1) register and is triggered by the 16th SCLK rising edge (last register bit is written). The switch time ends when a 1.5V DC bias level is measured on the selected RF port. It should be noted that this timing can vary due to delays with transitioning between the SPI clock domain and the internal operational clock domain. Figure 3 shows how the MUX switch time is measured from the 16th SCLK transition to the measured 1.5V DC bias on the RF port (tSW), to the DIR output transition (tSW-DIR), and to the first RXOUT bit (tSW-RX).

Figure 3. Switch Timing
Figure 4. RF Isolation

RF Isolation

The first form of separation to address is radio frequency signal isolation between RF ports. The primary implementation of the MAX11947 in a cellular tower application would have multiple RF frequencies in the cellular bands connected to separate ports on the 4:1 MUX. RF isolation describes how much of a high-frequency (cellular) signal on one RF port is detectable on another RF port. In Figure 4, an aggressor signal is applied to the coax cable tap of the P2 channel and the coax cable tap of P1 is measured for any impact on the victim channel. A majority of this isolation is provided by the lowpass filters on the P2 and P1 connections (LPF2 and LPF1, respectively).

AISG Isolation

The next form of separation to address is AISG carrier signal isolation between RF ports. Implementation of AISG v3.0 allows for the possibility of each RF port to carry either a multi-primary AISG signal or a PING signal. AISG isolation describes how much a 2.176MHz carrier signal on one RF port is detectable on another RF port. In Figure 5, an aggressor AISG signal is applied to the coax cable tap of the P2 channel and the coax cable tap of P1 is measured for any impact on the victim channel. A majority of this isolation is provided by 4:1 MUX switch within the MAX11947.

Figure 5. AISG Isolation

Modem Crosstalk

The last form of separation to address is modem crosstalk between RF ports. Again, implementation of AISG v3.0 allows for the possibility of each RF port to carry either a multi-primary AISG signal or a PING signal. Modem crosstalk describes how much a modulated AISG signal on a nonselected RF port is detectable by the MAX11947's internal receiver while connected to a different, selected RF port. In Figure 6, an aggressor AISG signal is applied to the coax cable tap of the P1 channel and the 4:1 MUX is connected to the P0 RF port. The aggressor signal is set to the maximum allowed power of +5dBm and the receiver threshold is set to the minimum programmed level of 0x0 (about -20.5dBm) and is monitored for any indication of a detected signal on the DIR or RXOUT pins. A majority of this isolation is provided by 4:1 MUX switch within the MAX11947.

Figure 6. Modem Crosstalk

Register Programming

The multiplexer is programmed through two register settings. In the MUX register (address 0x01), the OPEN bit internally disconnects the modem from the common port of the MUX, and the default condition (0x0) connects. In the same MUX register, the two RFPORT bits are used to select which external RF port the common port is connected to.

Table 1. RFPORT Register Settings
RFPORT VALUE COMMON CONNECTION
0x0 Connected to port P0
0x1 Connected to port P1
0x2 Connected to port P2
0x3 Connected to port P3
Internal Termination
The MAX11947 modem works in conjunction with a 4:1 multiplexer and an internal 50Ω termination. The termination is connected serially between the internal PA and the common MUX port. This resistor acts as series source for the transmit path (data flowing from TXIN to the selected RF port) and acts as parallel termination when data is being received on the internal receive path. The output of the transmitter is biased at 1.5V to maximize the power-supply rejection ratio and minimize any spurious emissions. It is recommended that the device be AC-coupled to the feeder cable through either an external RF filter or a series 100nF capacitor.
Receiver

The modem receiver consists of an LNA, a demodulator, and a sensitivity threshold adjustment system to convert the 2.176MHz OOK modulated signal into a digital output at RXOUT.

The maximum OOK input power at the internal LNA into the 50Ω internal termination is +5dBm. For a single-tone signal at 2.176MHz, +5dBm corresponds to 1.12VP-P.

Figure 7. Receiver Timing

Input Range and Sensitivity Threshold Control

The MAX11947 internal threshold is set to -15dBm (112.5mVP-P) by default (RXSENS set to 0xB). This centers the receive sensitivity threshold in the -12dBm to -18dBm undefined window specified by the AISG standard. This threshold sets the minimum input signal power recognized as an OOK ON carrier (asserting DIR level, logic-high and setting the RXOUT bit, logic-low).

Consider a corner case where the OOK signal at 2.176MHz present at the selected RF port, is at the minimum power of -15dBm ±3dB. To avoid saturation of the receiver input stage, any other adjacent carrier with power up-to +5dBm must be at a frequency below 1.25MHz or above 3.7MHz.

Referencing section 10.3.13 of the AISG v3.0 specification, ALD system designers are permitted to include splitters and/or combiners with an insertion loss of 4.5dB for a two-way split or as much as 6.3dB for a three-way split. With an outgoing transmission the MAX11947's adjustable transmitter power allows the designer to increase the modem output up to over +6dBm, which would result in an effective level of +1.7dBm or more after a two-way split (falling within the +3dBm ±2dB window). Similarly, an incoming transmission with a maximum signal power of +5dBm would have no issues being decoded at the modem receiver. However, the potentially minimum receive power of -12dBm may not be properly decoded after the 4.5dB splitter attenuation. The adjustable threshold of the MAX11947 allows the AISG designer to move the target from -15dBm to as low as -20.5dBm, effectively allowing a drop of 5.5dB which can accommodate the 4.5dB attenuation from a two-way splitter. See the In-Line Attenuation section for additional information.

The MAX11947 receiver sensitivity threshold can be varied with an internal register setting (RXSENS) from a default level of -15dBm down to -20.5dBm in about 0.5dB steps. To obtain the nominal sensitivity threshold of -15dBm at the RF port as the AISG standard requires, set RXSENS to 0xB (default value). For additional setting values and their equivalent threshold, see the RXTX register details.

Transmitter

The modem transmitter consists of a local oscillator (LO) circuit, an on-off-keyed (OOK) modulator, and an adjustable power amplifier (PA).

Figure 8. Transmitter Timing

Output Power Control

The MAX11947 output power can be varied with an internal register setting (TXPWR) from < 0dBm to over +6dBm (measured at the MUX selected RF port: P0, P1, P2, or P3) to compensate for loss in the external circuitry and cabling. The maximum voltage available at the MUX selected RF port is about 1.29VP-P. Assuming that the feeder cable is terminated into a 50Ω impedance, the external filter is lossless at 2.176MHz, where a series 50Ω termination is being used internally, the output level of 1.29VP-P corresponds to +6.2dBm at the feeder cable. See the External Low-Pass Filter and AC-Coupling to Feeder Cable section for more details.

The P_ voltage level can be varied according to the following equation:

POUT (at P_ in dBm) = TXPWR (decimal) x 0.5 (dB) - 0.5dBm

The output power has a soft ceiling around +6.0dBm at code 0x0D and rolls off the 0.5dB per code rate with the last two settings of 0x0E and 0x0F. The maximum PA output power is governed by the VCC supply and when using 5.0V the MAX11947 can likely achieve transmitter output power levels up to +7.0dBm.

To obtain the nominal power level of +3dBm at the feeder cable as the AISG standard requires, set TXPWR to 0x7 (default value), which provides about 0.89VP-P at the MUX selected RF port P_.

Carrier Tone
For a diagnostic tool, the transmitter can be held in a constant transmit mode by setting an internal register bit. By setting the TX_ON bit to a 1 value in the CFG (0x00) register, the transmitter sends a 2.176MHz carrier without a need to send a data stream through the TXIN pin. This bit is used for various production test and can be used on an AISG system to generate a carrier tone on the RF port selected with the MUX.
Direction Output

The MAX11947 provides a direction output pin (DIR) that indicates the direction of the data flow. This feature is very useful in the tower that acts as a slave in the AISG protocol. In most applications the base is the master and it controls the flow of data by performing bus arbitration. The output DIR allows the equipment in the tower to avoid any involvement in the bus arbitration. The Typical Application Circuit shows how the MAX11947 can be used in the tower in conjunction with the RS-485 transceiver such as the MAX13485E or MAX13486E.

Typically, the DIR output drives the DE (driver output enable) and RE_ (receiver output enable) of the RS-485 transceiver.

Whenever the data flows from the selected RF port (P0, P1, P2, or P3) to RXOUT, the DIR output is asserted high. When the MAX11947 is located in the tower, the data flow is being sent from the base (master) to the tower (slave). On the other side, when the data flows in the opposite direction, from TXIN to the selected RF port, the DIR output is deasserted low. However, the MAX11947 internal state machine is sensing both the TXIN and the status of the internal LNA, it can recognize the correct flow of data and avoid asserting the DIR high.

Figure 9 and Figure 10 show the timing diagrams of the DIR functionality. When the data flows from the selected RF port to RXOUT, DIR remains high for 16 bit times after the last logic-level low bit within the 8-bit protocol data (DIR dwell time). This is compliant with the AISG specification saying that the RS-485 transmitter stops driving the bus within 20 bit-times after the last stop bit is sent.

The DATARATE register value defines the duration of the bit time, as shown in Table 2.

Table 2. DATARATE Register Settings
DATARATE
VALUE
DATA RATE
(kbps)
BIT TIME
(μs)
DIR DWELL
TIME (ms)
0x0 (default) 9.6 104.16 1.667
0x1 38.4 26.04 0.416
0x2 115.2 8.68 0.139
0x3 N/A N/A N/A
Figure 9. Receiver Communication Flow
Figure 10. Transmitter Communication Flow
Serial Peripheral Interface (SPI)

The MAX11947 utilizes a 4-wire SPI protocol for programming its registers, configuring and controlling the operation of

the modem. The register contents can be read back through the SDO pin. The digital I/Os in Table 3.

control the operation of the SPI.

Table 3. SPI Pins
PIN DIRECTION DESCRIPTION
SCLK Input Serial Clock
SDI Input Serial Data Input (MOSI)
CSB Input Chip-Select Bar
SDO Output Serial Data Output (MISO)

Figure 11 shows a general SPI write transaction. Figure 12 show the format of a SPI read transaction. As shown in the diagrams, the R/W bit is set to 0 for a write transaction and the R/W bit is set to 1 for a read transaction.

Figure 11. SPI Write Transaction
Figure 12. SPI Read Transaction
Standby and Power-Down

Operational Modes

The MAX11947 has three modes of operation that include two power-saving modes. Each power-saving mode shuts down various internal blocks to save on current and reduce the overall power consumption of the modem. The SPI interface always remains operational, and the internal register values are always retained as long as the VCC and VL supplies remain within specified voltage limits.

Figure 13. Power Modes

Standby Mode

Setting the STANDBY bit in the CFG (0x00) register places the modem in standby mode. This configuration shuts down the transmitter signal chain including the TXIN interface, the modulator, the power amplifier, and all associated filtering blocks. While in the STANDBY state, the modem consumes less power and thus has a lower supply current. All other modem functions, including the receiver signal chain (RXOUT) and the DIR signal, continue to operate normally.

Power-Down Mode

Setting the PWRDN bit in the CFG (0x00) register places the MAX11947 modem into power-down mode. This configuration shuts down the transmitter signal chain as well as the receiver signal chain including the LNA, the demodulator, the RXOUT interface, and the DIR system.

Depending on the state of the XTALOSC bit in the CFG (0x00) register, the power-down mode maintains the crystal oscillator and SYNCOUT operation or shuts down those blocks as well. By default, the XTALOSC bit is set to 1 and the 8.704MHz system remains operational for cascaded master/slave clocking. See the Crystal and External Clock section. If the XTALOSC bit is set to 0 prior to or during the same write command as the PWRDN bit, the crystal oscillator and SYNCOUT blocks are also shut down while in power-down mode.

While in the PWRDN state, the modem consumes minimal power yet still retains values programmed in the registers and keeps the SPI interface operational for further programming and mode selection.

Port Scanning

The SCAN (0x02) register bits are used to configure the port scanning feature of the MAX11947. This state machine allows the modem to automatically listen for a carrier tone and/or the ping message on any of the RF ports sequentially. By setting the MASK_Px bits to 1 or 0, the individual RF ports can be included or excluded from the scan sequence, respectively. The default port scan process includes all RF ports (PINGCFG = 0x0F by default).

The automatic scanning process is initiated by setting the START_SCAN bit to 1; this is a self-clearing bit and reverts back to a 0 if the register is read back. While the modem is actively scanning the RF ports, the SCANNING bit asserts (1) and the LSTN_PORT bits indicate which port is connected to the modem through the 4:1 MUX.

Figure 14. Port Scan Flow Chart

The port scanning dwell time is either a manually controlled delay or is based on a combination of the SCAN_DWELL setting and the programmed DATARATE setting described in the Direction Output section. This dwell time defines how long the receiver listens to each RF port in order to detect a 2.176MHz carrier signal.

Table 4. SCAN_DWELL Time
SCAN_DWELL DWELL TIME
VALUE BIT PERIOD  MULTIPLIER DATA RATE =
0x0/9.6kbps
DATA RATE =
0x1/38.4kbps*
DATA RATE =
0x2/115.2kbps*
0x0 NA Manual mode: Sequenced by SCAN_INDEX Bit
0x1 1x 0.104ms 0.026ms 0.009ms
0x2 16x (Same as DIR Dwell) 1.667ms 0.416ms 0.139ms
0x3 User programmed Based on upper-nibble of PORTCFG (0x04) register and the DWELL_MULT (0x05) register
*Nonstandard setting for AISG v3.0

When SCAN_DWELL is set to 0x0, the dwell time is controlled by the user and does not increment to the next RF port until the SCAN_INDEX bit is set to 1 or a carrier signal is detected and FULL_DWELL is set to 0. This mode gives the user external, asynchronous control of the port scanning dwell time. When SCAN_DWELL is set to a value of 0x1 or 0x2, the scan dwell time is based on a fixed number of bit periods (1 or 16) based a combination of the SCAN_DWELL multiplier and the programmed data rate of the modem. When SCAN_DWELL is set to 0x3, a user-defined bit period multiplier between 1x to 4096x is used. The user defined DWELL multiplier is a 12-bit value spread across the PINGCFG (0x04) and DWELL_MULT (0x05) registers with the upper-nibble (bits 11:8) being programmed into the PINGCFG register and the remaining eight bits of the DWELL multiplier being programmed into the DWELL_MULT register.

Table 5. User-Programmed Dwell Time
PARAMETER DWELL VALUE
REGISTER / BITS BITS [11:8] BITS [7:4] BITS [3:0]
PINGCFG (0x04) [7:4]
DWELL_MULT (0x05) [7:4] [3:0]

The DATARATE value should be set prior to initiating the scan. See Table 4 and Table 5 for the available port scanning dwell times.

The port scanning engine indexes to the next port under three conditions:

  • After the dwell time has expired.
  • The SCAN_INDEX bit has been asserted by the user (in manual mode, SCAN_DWELL = 0x0).
  • An AISG carrier signal has been detected, FULL_DWELL = 0, and the CHK_ALL_PORTS = 1.

After one of the above conditions are met, the next unmasked RF port is selected and programmed into the MUX.

Each port is scanned in sequence from P0, to P1, P2, and P3 based on the mask selection. If the matching MASK_Px bit is set to 1 then that RF port Px is included in the scan sequence. If the MASK_Px bit is cleared 0, then that RF port will not be included in the sequence.

Once all the unmasked ports have been scanned, the SCANNING bit is set to 0 and the port scanning process is complete.

The port scanning process uses the sensitivity threshold programmed into the RXSENS bits of the RXTX (0x03) register. A signal is reported as a valid detection when the power level exceeds the programmed sensitivity threshold (i.e., the DIR pin indicates an AISG signal). See Input Range and Sensitivity Threshold Control in the Receiver section for more information. The RXSENS threshold should be set prior to initiating the scan.

When a carrier signal is detected, the port scanning engine continues to listen to that RF port if the FULL_DWELL bit is set to 1. This allows the user to decode a full message received at that port. The Rx channel remains active during port scanning thus the RXOUT pin indicates the received signal as in normal operation. For example, the AISG v3.0 ping packet is expected to have a length of 82 bits, assuming the DWELL time is set to 82x the bit period, the port scan routine remains on the selected RF port for the full time needed to decode such a ping message. See the Dwell Time section for for more information.

Results from the automatic port scanning are reported in the PORTSTAT (0x06) register. When an AISG carrier was detected during the scan, each port with a detected signal is marked with a 1 bit in the appropriate location (AISG_Px bit). If no carrier was detected during the dwell time on that port or by the time the SCAN_INDEX bit was asserted, the appropriate PORTSTAT bit has a 0 value.

The AISG_Px bits are only cleared when initiating a new scan. Results from previous scans are held and can be read from the PORTSTAT (0x06) register up until a new scan is started by setting the START_SCAN bit to 1.

Status Bits

The STATUS register (0x07) can be used to determine the state of various internal modem blocks. This read-only register indicates the status of the internal TXACTIVE signal, the RXOUT signal, and the DIR signal through the SPI interface rather than having to sense the three modem pins themselves.

The status of the PA can be determined by reading the TXACTIVE bit in the STATUS register. This bit provides the transmission status of the PA rather than the same logic value of the TXIN pin--effectively inverted from the pin logic.That is, when the TXIN pin is driven to a logic-low or 0 value OR the TX_ON bit of the CFG (0x00) register is set to 1, the transmitter generates a 2.176MHz carrier on the connected RF port and the TXACTIVE bit reads back as a 1.

The DIR bit [1] of the STATUS register provides a duplicate value of the DIR pin. That is, when the DIR pin is being driven to a logic-high or 1 value by the modem, indicating the receiver has detected a 2.176MHz carrier on the connected RF port, the DIR bit reads back as a 1.

The RXOUT bit [0] of the STATUS register also provides a duplicate value of the RXOUT pin. For example, when the receiver is detecting a 2.176MHz carrier on the connected RF port, the RXOUT pin is driven to a logic-low or 0 value by the modem and the RXOUT bit is also read back as a 0.