| PARAMETER | SYMBOL | CONDITIONS | MIN | TYP | MAX | UNITS |
|---|---|---|---|---|---|---|
| Supply Voltage | VCC | (Note 1) | 1.62 | 3.3 | 3.63 | V |
| Supply Current | ICC | Standby | 3.5 | 12 | μA | |
| Communicating (Note 2) | 60 | |||||
| I2C SCL AND SDA PINS (Note 3) | ||||||
| Low-Level Input Voltage | VIL | -0.3 | 0.3 × VCC | V | ||
| High-Level Input Voltage | VIH | VCC > 1.98V | 0.7 × VCC | VCC + 0.3 | V | |
| VCC ≤ 1.98V | 0.8 × VCC | VCC + 0.3 | ||||
| Hysteresis of Schmitt Trigger Inputs | VHYS | (Note 4) | 0.05 × VCC | V | ||
| Low-Level Output Voltage at 4mA Sink Current | VOL | (Note 5) | 0.4 | V | ||
| Output Fall Time from VIH(MIN) to VIL(MAX) with a Bus Capacitance from 10pF to 400pF | tOF | (Note 4) | 30 | ns | ||
| Pulse Width of Spikes that are Suppressed by the Input Filter | tSP | 50 | ns | |||
| Input Current with an Input Voltage Between 0.1VCC(MAX) and 0.9VCC(MAX) | II | (Note 4, Note 6) | -1 | +1 | µA | |
| Input Capacitance | CI | (Note 4) | 10 | pF | ||
| SCL Clock Frequency | fSCL | (Note 1) | 1 | MHz | ||
| Hold Time (Repeated) START Condition | tHD:STA | 0.45 | µs | |||
| Low Period of the SCL Clock | tLOW | (Note 7) | 0.65 | µs | ||
| High Period of the SCL Clock | tHIGH | 0.35 | µs | |||
| Setup Time for a Repeated START Condition | tSU:STA | 0.35 | µs | |||
| Data Hold Time | tHD:DAT | (Note 4, Note 7, Note 8) | 0.35 | µs | ||
| Data Setup Time | tSU:DAT | (Note 7, Note 9) | 100 | ns | ||
| Setup Time for STOP Condition | tSU:STO | 0.35 | µs | |||
| Bus Free Time Between a STOP and START Condition | tBUF | 0.6 | µs | |||
| Capacitive Load for Each Bus Line | CB | (Note 1, Note 10) | 400 | pF | ||
| Warm-Up Time | tOSCWUP | (Note 1, Note 11) | 1 | ms | ||
| CRYPTO FUNCTIONS | ||||||
| Computation Current | ICMP | 3 | mA | |||
| Read Memory Time | tRM | 5 | ms | |||
| Write Memory Time | tWM | 60 | ms | |||
| Short Write Memory Time | tWMS | 15 | ms | |||
| Computation Time | tCMP | 15 | ms | |||
| EEPROM | ||||||
| Write/Erase Cycles (Endurance) | NCY | (Note 12) | 100k | |||
| Data Retention | tDR | TA = +85ºC (Note 13) | 10 | years | ||
| Note 1: | System requirement. |
| Note 2: | Operating current during I2C communication at 1MHz with < 25ns rise and fall times on SDA and SCL. |
| Note 3: | All I2C timing values are referred to VIH(MIN) and VIL(MAX) levels. |
| Note 4: | Guaranteed by design and/or characterization only. Not production tested. |
| Note 5: | The I-V characteristic is linear for voltages less than 1V. |
| Note 6: | I/O pins of the DS28C16 do not obstruct the SDA and SCL lines if VCC is switched off. |
| Note 7: | tLOW min = tHD:DAT max + 200ns for rise or fall time + tSU:DAT min. Values greater than these can be accommodated by extending tLOW accordingly. |
| Note 8: | The DS28C16 provides a hold time of at least 100ns for the SDA signal (referenced to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. |
| Note 9: | The DS28C16 can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250ns must then be met. Also, the acknowledge timing must meet this setup time (I2C bus specification Rev. 03, 19 June 2007). |
| Note 10: | CB = Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application (I2C bus specification Rev. 03, 19 June 2007). |
| Note 11: | I2C communication should not take place for at least tOSCWUP after VCC reaches VCC(MIN). |
| Note 12: | Write-cycle endurance is tested in compliance with JESD47H. |
| Note 13: | Data retention is tested in compliance with JESD47H. |
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